专利名称：Method and apparatus for performing
extraction on an integrated circuit designwith support vector machines
发明人：Steven Teig,Arindam Chatterjee申请号：US10334664申请日：20021231公开号：US06925618B1公开日：20050802
专利附图：
摘要：The present invention introduces novel methods of performing integratedcircuit layout extraction. In the system of the present invention, a complex extraction
problem is first broken down into a set of smaller extraction sub problems. Some of thesmaller extraction sub problems may be handled by simple parametric models. However,for the frequent complex extraction sub problems, machine learning is used to buildmodels. Specifically, Support Vector Machines are constructed to extract the desiredelectrical characteristics. To build the Support Vector Machines, Experimental design isemployed to select a set of training points that provide the best information. In oneembodiment, the training point set is created by creating a critical input spanning set,adding training points from critical regions in the input space, and adding training pointsfrom frequently encountered profile cases. The training point set is then used to trainthe Support Vector Machine that will extract electrical characteristics for the extractionsub problem.
申请人：Steven Teig,Arindam Chatterjee
地址：Menlo Park CA US,San Carlos CA US
国籍：US,US
代理机构：Stattler Johansen & Adeli LLP
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