专利名称：Method and apparatus for performing
extraction on an integrated circuit design
发明人：Steven Teig,Arindam Chatterjee申请号：US10335095申请日：20021231公开号：US06941531B1公开日：20050906
专利附图：
摘要：The present invention introduces novel methods of performing integratedcircuit layout extraction. In the system of the present invention, a complex extractionproblem is first broken down into a set of smaller extraction sub problems. Some of the
smaller extraction sub problems may be handled by simple parametric models. Forexample, extracting the resistance from a straight section of interconnect wire may beperformed by multiplying a known resistance per unit length by the length of thestraight section of interconnect wire. For more complex extraction sub problems,machine learning is used to build models. In one embodiment, Support Vector Machinesare constructed to extract the desired electrical characteristics.
申请人：Steven Teig,Arindam Chatterjee
地址：Menlo Park CA US,San Carlos CA US
国籍：US,US
代理机构：Stattler, Johansen & Adeli LLP
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