·ToolsInformation·FAQs
·ApplicationNote
-HA0004EHT48&HT46MCUUARTSoftwareImplementationMethod-HA0005EControllingtheI2CbuswiththeHT48&HT46MCUSeries-HA0013EHT48&HT46LCMInterfaceDesign
-HA0047EAnPWMapplicationexampleusingtheHT46seriesofMCUs-HA0075EMCUResetandOscillatorCircuitsApplicationNote
Features
·Operatingvoltage:
·Upto0.5msinstructioncyclewith8MHzsystemclock
fSYS=4MHz:2.2V~5.5VfSYS=8MHz:3.3V~5.5V
·23bidirectionalI/Olines(max.)·1interruptinputsharedwithanI/Oline·16-bitprogrammabletimer/eventcounterwith
atVDD=5V
·8-levelsubroutinenesting
·8channels10-bitresolutionA/Dconverter
·2-channel8-bitPWMoutputsharedwithtwoI/Olines·Bitmanipulationinstruction·15-bittablereadinstruction·63powerfulinstructions
·Allinstructionsinoneortwomachinecycles·Lowvoltageresetfunction·I2CBus(slavemode)
·24/28-pinSKDIP/SOPpackages
overflowinterruptand7-stageprescaler
·On-chipcrystalandRCoscillator·WatchdogTimer
·4096´15programmemory·192´8datamemoryRAM
·SupportsPFDforsoundgeneration
·HALTfunctionandwake-upfeaturereducepower
consumption
GeneralDescription
TheHT46R23/HT46C23are8-bit,highperformance,RISCarchitecturemicrocontrollerdevicesspecificallydesignedforA/Dapplicationsthatinterfacedirectlytoanalogsignals,suchasthosefromsensors.ThemaskversionHT46C23isfullypinandfunctionallycompatiblewiththeOTPversionHT46R23device.
Theadvantagesoflowpowerconsumption,I/Oflexibil-ity,programmablefrequencydivider,timerfunctions,oscillatoroptions,multi-channelA/DConverter,PulseWidthModulationfunction,I2Cinterface,HALTandwake-upfunctions,enhancetheversatilityofthesede-vicestosuitawiderangeofA/Dapplicationpossibilitiessuchassensorsignalprocessing,motordriving,indus-trialcontrol,consumerproducts,subsystemcontrollers,etc.
I2CisatrademarkofPhilipsSemiconductors.
Rev.2.111December29,2008
HT46R23/HT46C23BlockDiagram
PinAssignment
Rev.2.112December29,2008
HT46R23/HT46C23PadDescription
PadNamePA0~PA2PA3/PFDPA4/TMRPA5/INTPA6/SDAPA7/SCLPB0/AN0PB1/AN1PB2/AN2PB3/AN3PB4/AN4PB5/AN5PB6/AN6PB7/AN7PC0~PC4
I/O
OptionPull-highWake-upPA3orPFDI/OorSerialBus
Description
Bidirectional8-bitinput/outputport.Eachbitcanbeconfiguredaswake-upinputbyoptions.SoftwareinstructionsdeterminetheCMOSoutputorSchmitttriggerinputwithorwithoutpull-highresistor(determinedbypull-highoptions:bitoption).ThePFD,TMRandINTarepin-sharedwithPA3,PA4andPA5,respectively.OncetheI2CBusfunctionisused,thein-ternalregistersrelatedtoPA6andPA7cannotbeused.
I/O
I/OPull-high
Bidirectional8-bitinput/outputport.SoftwareinstructionsdeterminetheCMOSoutput,Schmitttriggerinputwithorwithoutpull-highresistor(deter-minedbypull-high:portoption)orA/Dinput.
OnceaPBlineisselectedasanA/Dinput(byusingsoftwarecontrol),theI/Ofunctionandpull-highresistoraredisabledautomatically.
I/OPull-high
Bidirectional5-bitinput/outputport.SoftwareinstructionsdeterminetheCMOSoutput,Schmitttriggerinputwithorwithoutpull-highresistor(deter-minebypull-highoption:portoption).
Bidirectional2-bitinput/outputport.SoftwareinstructionsdeterminetheCMOSoutput,Schmitttriggerinputwithorwithoutapull-highresistor(de-terminedbypull-highoption:portoption).ThePWM0/PWM1outputfunc-tionarepin-sharedwithPD0/PD1(dependentonPWMoptions).Schmitttriggerresetinput.Activelow.Positivepowersupply
Negativepowersupply,ground.
OSC1,OSC2areconnectedtoanRCnetworkoraCrystal(determinedbyoptions)fortheinternalsystemclock.InthecaseofRCoperation,OSC2istheoutputterminalfor1/4systemclock.TESTmodeinputpin.
Itdisconnectsinnormaloperation.
PD0/PWM0PD1/PWM1RESVDDVSSOSC1OSC2TEST1TEST2TEST3
I/O
Pull-highI/OorPWM
¾¾¾CrystalorRC
I¾¾IO
I¾
AbsoluteMaximumRatings
SupplyVoltage...........................VSS-0.3VtoVSS+6.0VInputVoltage..............................VSS-0.3VtoVDD+0.3V
StorageTemperature............................-50°Cto125°COperatingTemperature...........................-40°Cto85°C
Note:Thesearestressratingsonly.Stressesexceedingtherangespecifiedunder²AbsoluteMaximumRatings²may
causesubstantialdamagetothedevice.Functionaloperationofthisdeviceatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicereliabil-ity.
Rev.2.113December29,2008
HT46R23/HT46C23D.C.Characteristics
Symbol
Parameter
TestConditionsVDD¾¾3V5V3V5V5V3V5V3V5V¾¾¾¾¾3V5V3V5V3V5V¾¾3V5V
ConditionsfSYS=4MHzfSYS=8MHz
Noload,fSYS=4MHzADCdisableNoload,fSYS=4MHzADCdisableNoload,fSYS=8MHzADCdisable
Noload,systemHALT
Min.2.23.3¾¾¾¾¾¾¾¾¾00.7VDD
00.9VDD2.7410-2-520100¾¾¾
Typ.¾¾0.620.82.54¾¾¾¾¾¾¾¾3820-4-106030¾±0.50.51.5
Max.5.55.51.541.548510120.3VDDVDD0.4VDDVDD3.3¾¾¾¾10050VDD±113
Ta=25°CUnitVVmAmAmAmAmAmAmAmAmAVVVVVmAmAmAmAkWkWVLSBmAmA
VDDOperatingVoltageOperatingCurrent(CrystalOSC)OperatingCurrent(RCOSC)
OperatingCurrent
(CrystalOSC,RCOSC)StandbyCurrent(WDTEnabled)StandbyCurrent(WDTDisabled)
InputLowVoltageforI/OPorts,TMRandINT
InputHighVoltageforI/OPorts,TMRandINTInputLowVoltage(RES)InputHighVoltage(RES)LowVoltageResetI/OPortSinkCurrent
IDD1
IDD2IDD3ISTB1
ISTB2VIL1VIH1VIL2VIH2VLVRIOL
Noload,systemHALT
¾¾¾¾¾
VOL=0.1VDDVOL=0.1VDDVOH=0.9VDDVOH=0.9VDD
¾¾¾¾¾
IOHI/OPortSourceCurrent
RPHVADEADIADC
Pull-highResistanceA/DInputVoltageA/DConversionError
AdditionalPowerConsumptionifA/DConverterisUsed
Rev.2.114December29,2008
HT46R23/HT46C23A.C.Characteristics
Symbol
Parameter
TestConditionsVDD¾¾¾¾3V5V¾¾¾¾¾¾¾
Conditions2.2V~5.5V3.3V~5.5V2.2V~5.5V3.3V~5.5V
¾¾¾
Wake-upfromHALT
¾¾¾¾
Connecttoexternalpull-highresistor2kW
Min.4004000045321¾11¾¾64
Typ.¾¾¾¾9065¾1024¾¾7632¾
Max.4000800040008000180130¾¾¾¾¾¾¾
Ta=25°CUnitkHzkHzkHzkHzmsmsms*tSYSmsmstADtAD*tSYS
fSYSSystemClockTimerI/PFrequency(TMR)
WatchdogOscillatorPeriodExternalResetLowPulseWidthSystemStart-upTimerPeriodInterruptPulseWidthA/DClockPeriodA/DConversionTimeA/DSamplingTimeI2CBusClockPeriod
fTIMER
tWDTOSCtREStSSTtINTtADtADCtADCStIIC
Note:*tSYS=1/fSYS
Rev.2.115December29,2008
HT46R23/HT46C23FunctionalDescription
ExecutionFlow
ThesystemclockforthemicrocontrollerisderivedfromeitheracrystaloranRCoscillator.Thesystemclockisinternallydividedintofournon-overlappingclocks.Oneinstructioncycleconsistsoffoursystemclockcycles.Instructionfetchingandexecutionarepipelinedinsuchawaythatafetchtakesaninstructioncyclewhilede-codingandexecutiontakesthenextinstructioncycle.However,thepipeliningschemecauseseachinstruc-tiontoeffectivelyexecuteinacycle.Ifaninstructionchangestheprogramcounter,twocyclesarerequiredtocompletetheinstruction.ProgramCounter-PC
Theprogramcounter(PC)controlsthesequenceinwhichtheinstructionsstoredinprogramPROMareexe-cutedanditscontentsspecifyfullrangeofprogrammemory.
Afteraccessingaprogrammemorywordtofetchanin-structioncode,thecontentsoftheprogramcounterarein-crementedbyone.Theprogramcounterthenpointstothememorywordcontainingthenextinstructioncode.
Whenexecutingajumpinstruction,conditionalskipex-ecution,loadingPCLregister,subroutinecall,initialre-set,internalinterrupt,externalinterruptorreturnfromsubroutine,thePCmanipulatestheprogramtransferbyloadingtheaddresscorrespondingtoeachinstruction.Theconditionalskipisactivatedbyinstructions.Oncetheconditionismet,thenextinstruction,fetchedduringthecurrentinstructionexecution,isdiscardedandadummycyclereplacesittogettheproperinstruction.Otherwiseproceedwiththenextinstruction.
Thelowerbyteoftheprogramcounter(PCL)isaread-ableandwriteableregister(06H).MovingdataintothePCLperformsashortjump.Thedestinationwillbewithin256locations.
Whenacontroltransfertakesplace,anadditionaldummycycleisrequired.ProgramMemory-ROM
Theprogrammemoryisusedtostoretheprogramin-structionswhicharetobeexecuted.Italsocontainsdata,table,andinterruptentries,andisorganizedinto4096´15bits,addressedbytheprogramcounterandta-blepointer.
ExecutionFlow
ProgramCounter
*1100000*11#11S11
*1000000*10#10S10
*900000*9#9S9
*800000*8#8S8
*700000@7#7S7
*600000@6#6S6
*500000@5#5S5
*400001@4#4S4
*300110@3#3S3
*201010@2#2S2
*100000@1#1S1
*000000@0#0S0
Mode
InitialResetExternalInterrupt
Timer/EventCounterOverflowA/DConverterInterruptI2CBusInterruptSkipLoadingPCLJump,CallBranchReturnfromSubroutine
ProgramCounter+2
ProgramCounter
Note:
*11~*0:Programcounterbits#11~#0:Instructioncodebits
6
S11~S0:Stackregisterbits@7~@0:PCLbits
December29,2008
Rev.2.11
HT46R23/HT46C23Certainlocationsintheprogrammemoryarereservedforspecialusage:
·Location000H
Thisareaisreservedforprograminitialization.Afterchipreset,theprogramalwaysbeginsexecutionatlo-cation000H.
·Location004H
Thisareaisreservedfortheexternalinterruptserviceprogram.IftheINTinputpinisactivated,theinterruptisenabledandthestackisnotfull,theprogrambeginsexecutionatlocation004H.
·Location008H
Thisareaisreservedforthetimer/eventcounterinter-ruptserviceprogram.Ifatimerinterruptresultsfromatimer/eventcounteroverflow,andiftheinterruptisen-abledandthestackisnotfull,theprogrambeginsexe-cutionatlocation008H.
·Location00CH
ThisareaisreservedfortheA/Dconverterinterruptserviceprogram.IfanA/DconverterinterruptresultsfromanendofA/Dconversion,andiftheinterruptisenabledandthestackisnotfull,theprogrambeginsexecutionatlocation00CH.
·Location010H
ProgramMemory
changedbythetablereadinstructionusedintheISR.Errorscanoccur.Inotherwords,usingthetablereadinstructioninthemainroutineandtheISRsimulta-neouslyshouldbeavoided.However,ifthetablereadinstructionhastobeappliedinboththemainroutineandtheISR,theinterruptissupposedtobedisabledpriortothetablereadinstruction.ItwillnotbeenableduntiltheTBLHhasbeenbackedup.Alltablerelatedinstructionsrequiretwocyclestocompletetheopera-tion.Theseareasmayfunctionasnormalprogrammemorydependingupontherequirements.StackRegister-STACK
Thisisaspecialpartofthememorywhichisusedtosavethecontentsoftheprogramcounter(PC)only.Thestackisorganizedinto8levelsandisneitherpartofthedatanorpartoftheprogramspace,andisneitherread-ablenorwriteable.Theactivatedlevelisindexedbythestackpointer(SP)andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgment,thecontentsoftheprogramcounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction(RETorRETI),thepro-gramcounterisrestoredtoitspreviousvaluefromthestack.Afterachipreset,theSPwillpointtothetopofthestack.
ThisareaisreservedfortheI2CBusinterruptserviceprogram.IftheI2CBusinterruptresultingfromaslaveaddressismatchorcompletedonebyteofdatatrans-fer,andiftheinterruptisenableandthestackisnotfull,theprogrambeginsexecutionatlocation010H.AnylocationinthePROMspacecanbeusedaslook-uptables.Theinstructions²TABRDC[m]²(thecurrentpage,1page=256words)and²TABRDL[m]²(thelastpage)transferthecontentsofthelower-orderbytetothespecifieddatamemory,andthehigher-orderbytetoTBLH(08H).Onlythedestinationofthelower-orderbyteinthetableiswell-defined,theotherbitsofthetablewordaretransferredtothelowerportionofTBLH,andtheremaining1bitisreadas²0².TheTableHigher-orderbyteregister(TBLH)isreadonly.Thetablepointer(TBLP)isaread/writeregister(07H),whichindicatesthetablelocation.Beforeac-cessingthetable,thelocationmustbeplacedinTBLP.TheTBLHisreadonlyandcannotberestored.IfthemainroutineandtheISR(InterruptServiceRou-tine)bothemploythetablereadinstruction,thecon-tentsoftheTBLHinthemainroutinearelikelytobe
·Tablelocation
InstructionTABRDC[m]TABRDL[m]
TableLocation
*11P111
*10P101
*9P91
*8P81
*7@7@7
*6@6@6
*5@5@5
*4@4@4
*3@3@3
*2@2@2
*1@1@1
*0@0@0
TableLocation
Note:
*11~*0:Tablelocationbits@7~@0:Tablepointerbits
P11~P8:Currentprogramcounterbits
Rev.2.117December29,2008
HT46R23/HT46C23Ifthestackisfullandanon-maskedinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgmentwillbeinhibited.Whenthestackpointerisdecremented(byRETorRETI),theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowal-lowingtheprogrammertousethestructuremoreeasily.Inasimilarcase,ifthestackisfullanda²CALL²issub-sequentlyexecuted,stackoverflowoccursandthefirstentrywillbelost(onlythemostrecent8returnad-dressesarestored).DataMemory-RAM
Thedatamemoryisdesignedwith224´8bits.Thedatamemoryisdividedintotwofunctionalgroups:spe-cialfunctionregistersandgeneralpurposedatamem-ory(192´8).Mostareread/write,butsomearereadonly.
Thespecialfunctionregistersincludetheindirectad-dressingregisters(00H;02H),timer/eventcounterhigher-orderbyteregister(TMRH;0CH),timer/eventcounterlow-orderbyteregister(TMRL;0DH),timer/eventcountercontrolregister(TMRC;0EH),pro-gramcounterlower-orderbyteregister(PCL;06H),memorypointerregisters(MP0;01H,MP1;03H),accu-mulator(ACC;05H),tablepointer(TBLP;07H),tablehigher-orderbyteregister(TBLH;08H),statusregister(STATUS;0AH),interruptcontrolregister0(INTC0;0BH),PWMdataregister(PWM0;1AH,PWM1;1BH),theI2CBusslaveaddressregister(HADR;20H),theI2CBuscontrolregister(HCR;21H),theI2CBusstatusreg-ister(HSR;22H),theI2CBusdataregister(HDR;23H),theA/Dresultlower-orderbyteregister(ADRL;24H),theA/Dresulthigher-orderbyteregister(ADRH;25H),theA/Dcontrolregister(ADCR;26H),theA/Dclocksettingregister(ACSR;27H),I/Oregisters(PA;12H,PB;14H,PC;16H,PD;18H)andI/Ocontrolregisters(PAC;13H,PBC;15H,PCC;17H,PDC;19H).Theremainingspacebeforethe40Hisreservedforfutureexpandedusageandreadingtheselocationswillget²00H².Thegeneralpurposedatamemory,addressedfrom40HtoFFH,isusedfordataandcontrolinformationunderinstructioncommands.
Allofthedatamemoryareascanhandlearithmetic,logic,increment,decrementandrotateoperationsdi-rectly.Exceptforsomededicatedbits,eachbitinthedatamemorycanbesetandresetby²SET[m].i²and²CLR[m].i².Theyarealsoindirectlyaccessiblethroughmemorypointerregisters(MP0;01H/MP1;03H).IndirectAddressingRegister
Location00Hand02Hareindirectaddressingregistersthatarenotphysicallyimplemented.Anyread/writeop-erationof[00H]or[02H]willaccessdatamemorypointedtobyMP0[01H]orMP1[03H]respectively.Readinglocation00Hor02Hitselfindirectlywillreturntheresult00H.Writingindirectlyresultinnooperation.Rev.2.11
8
Thememorypointerregisters(MP0andMP1are8-bitregisters).Accumulator
TheaccumulatoriscloselyrelatedtoALUoperations.Itisalsomappedtolocation05Hofthedatamemoryandcancarryoutimmediatedataoperations.Thedatamovementbetweentwodatamemorylocationsmustpassthroughtheaccumulator.
RAMMapping
December29,2008
HT46R23/HT46C23ArithmeticandLogicUnit-ALU
Thiscircuitperforms8-bitarithmeticandlogicoperations.TheALUprovidesthefollowingfunctions:
·Arithmeticoperations(ADD,ADC,SUB,SBC,DAA)·Logicoperations(AND,OR,XOR,CPL)·Rotation(RL,RR,RLC,RRC)·IncrementandDecrement(INC,DEC)·Branchdecision(SZ,SNZ,SIZ,SDZ....)
Interrupt
Thedeviceprovidesanexternalinterrupt,aninternaltimer/eventcounterinterrupt,theA/DconverterinterruptandtheI2CBusinterrupts.Theinterruptcontrolregister0(INTC0;0BH)andinterruptcontrolregister1(INTC1;1EH)containstheinterruptcontrolbitstosettheenableordisableandtheinterruptrequestflags.Onceaninterruptsubroutineisserviced,alltheotherin-terruptswillbeblocked(byclearingtheEMIbit).Thisschememaypreventanyfurtherinterruptnesting.Otherinterruptrequestsmayhappenduringthisintervalbutonlytheinterruptrequestflagisrecorded.Ifacertainin-terruptrequiresservicingwithintheserviceroutine,theEMIbitandthecorrespondingbitofINTC0andINTC1maybesettoallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheSPisdecremented.Ifimmediateserviceisdesired,thestackmustbepre-ventedfrombecomingfull.
Allthesekindsofinterruptshaveawake-upcapability.Asaninterruptisserviced,acontroltransferoccursbypushingtheprogramcounterontothestack,followedbyabranchtoasubroutineatspecifiedlocationinthepro-grammemory.Onlytheprogramcounterispushedontothestack.Ifthecontentsoftheregisterorstatusregister(STATUS)arealteredbytheinterruptserviceprogramwhichcorruptsthedesiredcontrolsequence,thecon-tentsshouldbesavedinadvance.
Externalinterruptsaretriggeredbyahightolowtransi-tionofINTandtherelatedinterruptrequestflag(EIF;bit4ofINTC0)willbeset.Whentheinterruptisenabled,thestackisnotfullandtheexternalinterruptisactive,asubroutinecalltolocation04Hwilloccur.Theinterruptrequestflag(EIF)andEMIbitswillbeclearedtodisableotherinterrupts.
TheALUnotonlysavestheresultsofadataoperationbutalsochangesthestatusregister.StatusRegister-STATUS
This8-bitregister(0AH)containsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Italsorecordsthestatusinformationandcontrolstheoperationsequence.
WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddi-tionoperationsrelatedtothestatusregistermaygivedifferentresultsfromthoseintended.TheTOflagcanbeaffectedonlybysystempower-up,aWDTtime-outorexecutingthe²CLRWDT²or²HALT²in-struction.ThePDFflagcanbeaffectedonlybyexe-cutingthe²HALT²or²CLRWDT²instructionorasystempower-up.
TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.
Inaddition,onenteringtheinterruptsequenceorexe-cutingthesubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusareimportantandifthesubroutinecancor-ruptthestatusregister,precautionsmustbetakentosaveitproperly.BitNo.0
LabelC
Function
Cissetiftheoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyaro-tatethroughcarryinstruction.
ACissetiftheoperationresultsinacarryoutofthelownibblesinadditionornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.
Zissetiftheresultofanarithmeticorlogicoperationiszero;otherwiseZiscleared.OVissetiftheoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.
PDFisclearedbysystempower-uporexecutingthe²CLRWDT²instruction.PDFissetbyexecutingthe²HALT²instruction.
TOisclearedbysystempower-uporexecutingthe²CLRWDT²or²HALT²instruction.TOissetbyaWDTtime-out.Unusedbit,readas²0²
Status(0AH)Register
123456,7
ACZOVPDFTO¾
Rev.2.119December29,2008
HT46R23/HT46C23Theinternaltimer/eventcounterinterruptisinitializedbysettingthetimer/eventcounterinterruptrequestflag(TF;bit5ofINTC0),causedbyatimeroverflow.Whentheinterruptisenabled,thestackisnotfullandtheTFbitisset,asubroutinecalltolocation08Hwilloccur.Therelatedinterruptrequestflag(TF)willberesetandtheEMIbitclearedtodisablefurtherinterrupts.
TheA/DconverterinterruptisinitializedbysettingtheA/Dconverterrequestflag(ADF;bit6ofINTC0),causedbyanendofA/Dconversion.Whentheinterruptisenabled,thestackisnotfullandtheADFisset,asub-routinecalltolocation0CHwilloccur.Therelatedinter-ruptrequestflag(ADF)willberesetandtheEMIbitclearedtodisablefurtherinterrupts.BitNo.Label01
EMIEEI
Function
Controlsthemaster(global)interrupt(1=enabled;0=disabled)Controlstheexternalinterrupt(1=enabled;0=disabled)Controlsthetimer/eventcounterinterrupt
(1=enabled;0=disabled)
ControlstheA/Dconverterinterrupt(1=enabled;0=disabled)Externalinterruptrequestflag(1=active;0=inactive)
Internaltimer/eventcounterrequestflag
(1=active;0=inactive)A/Dconverterrequestflag(1=active;0=inactive)
Fortestmodeusedonly.
Mustbewrittenas²0²;otherwisemayresultinunpredictableoperation.INTC0(0BH)Register
TheI2CBusinterruptisinitializedbysettingtheI2CBusinterruptrequestflag(HIF;bit4ofINTC1),causedbyaslaveaddressmatch(HAAS=²1²)oronebyteofdatatrans-feriscompleted.Whentheinterruptisenabled,thestackisnotfullandtheHIFbitisset,asubroutinecalltolocation10Hwilloccur.Therelatedinterruptrequestflag(HIF)willberesetandtheEMIbitclearedtodisablefurtherinter-rupts.
Duringtheexecutionofaninterruptsubroutine,otherin-terruptacknowledgmentsarehelduntilthe²RETI²in-structionisexecutedortheEMIbitandtherelatedinterruptcontrolbitaresetto1(ofcourse,ifthestackisnotfull).Toreturnfromtheinterruptsubroutine,²RET²or
45~7
HIF¾
²RETI²maybeinvoked.RETIwillsettheEMIbittoen-ableaninterruptservice,butRETwillnot.
Interrupts,occurringintheintervalbetweentherisingedgesoftwoconsecutiveT2pulses,willbeservicedonthelatterofthetwoT2pulses,ifthecorrespondinginter-ruptsareenabled.Inthecaseofsimultaneousrequeststhefollowingtableshowstheprioritythatisapplied.ThesecanbemaskedbyresettingtheEMIbit.
InterruptSource
ExternalInterrupt
Timer/EventCounterOverflowA/DConverterInterruptSerialbusinterrupt
Priority1234
Vector04H08H0CH10H
2ETI
34
EADIEIF
5TF
Thetimer/eventcounterinterruptrequestflag(TF),ex-ternalinterruptrequestflag(EIF),A/Dconverterrequestflag(ADF),theI2CBusinterruptrequestflag(HIF),en-abletimer/eventcounterbit(ETI),enableexternalinter-ruptbit(EEI),enableA/Dconverterinterruptbit(EADI),enableI2CBusinterruptbit(EHI)andenablemasterin-terruptbit(EMI)constituteaninterruptcontrolregister0(INTC0)andaninterruptcontrolregister1(INTC1)whicharelocatedat0BHand1EHinthedatamemory.EMI,EEI,ETI,EADI,EHIareusedtocontroltheen-abling/disablingofinterrupts.Thesebitspreventthere-questedinterruptfrombeingserviced.Oncetheinterruptrequestflags(TF,EIF,ADF,HIF)areset,theywillremainintheINTC0andINTC1registeruntilthein-terruptsareservicedorclearedbyasoftwareinstruc-tion.BitNo.01~3
LabelEHI¾
Function
ControlstheI2CBusinterrupt(1=enabled;0=disabled)Unusedbit,readas²0²I2CBusinterruptrequestflag(1=active;0=inactive)Unusedbit,readas²0²INTC1(1EH)Register
Itisrecommendedthataprogramdoesnotusethe²CALLsubroutine²withintheinterruptsubroutine.In-terruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediatelyinsomeapplications.Ifonlyonestackisleftandenablingtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedam-agedoncethe²CALL²operatesintheinterruptsubrou-tine.
6ADF
7¾
Rev.2.1110December29,2008
HT46R23/HT46C23OscillatorConfiguration
Therearetwooscillatorcircuitsinthemicrocontroller.
(systemclockdividedby4)decidedbyoptions.Thistimerisdesignedtopreventasoftwaremalfunctionorsequencejumpingtoanunknownlocationwithunpre-dictableresults.Thewatchdogtimercanbedisabledbyanoption.Ifthewatchdogtimerisdisabled,alltheexe-cutionsrelatedtotheWDTresultinnooperation.OnceaninternalWDToscillator(RCoscillatorwithpe-riod65ms/@5Vnormally)isselected,itisdividedby212~215(byoptionstogettheWDTtime-outperiod).TheminimumperiodofWDTtime-outperiodisabout300ms~600ms.Thistime-outperiodmayvarywithtem-perature,VDDandprocessvariations.ByselectiontheWDToptions,longertime-outperiodscanberealized.IftheWDTtime-outisselected215,themaximumtime-outperiodisdividedby215~216about2.1s~4.3s.
IftheWDToscillatorisdisabled,theWDTclockmaystillcomefromtheinstructionclockandoperateinthesamemannerexceptthatinthehaltstatetheWDTmaystopcountingandloseitsprotectingpurpose.Inthissituationthelogiccanonlyberestartedbyexternallogic.Ifthedeviceoperatesinanoisyenvironment,usingtheon-chipRCoscillator(WDTOSC)isstronglyrecom-mended,sincetheHALTwillstopthesystemclock.TheWDToverflowundernormaloperationwillinitialize²chipreset²andsetthestatusbitTO.Whereasinthehaltmode,theoverflowwillinitializea²warmreset²onlytheprogramcounterandstackpointerareresettozero.ToclearthecontentsofWDT,threemethodsareadopted;ex-ternalreset(alowleveltoRES),softwareinstructions,oraHALTinstruction.ThesoftwareinstructionsincludeCLRWDTandtheotherset-CLRWDT1andCLRWDT2.Ofthesetwotypesofinstruction,onlyonecanbeactivede-pendingontheoptions-²CLRWDTtimesselectionop-tion².Ifthe²CLRWDT²isselected(i.e.CLRWDTtimesequalone),anyexecutionoftheCLRWDTinstructionwillcleartheWDT.Incase²CLRWDT1²and²CLRWDT2²arechosen(i.e.CLRWDTtimesequaltwo),thesetwoin-structionsmustbeexecutedtocleartheWDT;otherwise,theWDTmayresetthechipbecauseoftime-out.IftheWDTtime-outperiodisselectedfs/212(byoptions),theWDTtime-outperiodrangesfromfs/212~fs/213,sincethe²CLRWDT²or²CLRWDT1²and²CLRWDT2²in-structionsonlyclearthelasttwostagesoftheWDT.
SystemOscillator
Botharedesignedforsystemclocks,namelytheRCos-cillatorandtheCrystaloscillator,whicharedeterminedbyoptions.Nomatterwhatoscillatortypeisselected,thesignalprovidesthesystemclock.TheHALTmodestopsthesystemoscillatorandignoresanexternalsig-naltoconservepower.
IfanRCoscillatorisused,anexternalresistorbetweenOSC1andVSSisrequiredandtheresistancemustrangefrom30kWto750kW.Thesystemclock,dividedby4,isavailableonOSC2withpull-highresistor,whichcanbeusedtosynchronizeexternallogic.TheRCoscillatorprovidesthemostcosteffectivesolution.However,thefrequencyofoscillationmayvarywithVDD,tempera-turesandthechipitselfduetoprocessvariations.Itis,therefore,notsuitablefortimingsensitiveoperationswhereanaccurateoscillatorfrequencyisdesired.IftheCrystaloscillatorisused,acrystalacrossOSC1andOSC2isneededtoprovidethefeedbackandphaseshiftrequiredfortheoscillator,andnootherexternalcomponentsarerequired.Insteadofacrystal,aresona-torcanalsobeconnectedbetweenOSC1andOSC2togetafrequencyreference,buttwoexternalcapacitorsinOSC1andOSC2arerequired(Iftheoscillatingfre-quencyislessthan1MHz).
TheWDToscillatorisafreerunningon-chipRCoscilla-tor,andnoexternalcomponentsarerequired.Evenifthesystementersthepowerdownmode,thesystemclockisstopped,buttheWDToscillatorstillworkswithaperiodofapproximately65ms@5V.TheWDToscillatorcanbedisabledbyoptionstoconservepower.WatchdogTimer-WDT
TheclocksourceoftheWDTisimplementedbyandedi-catedRCoscillator(WDToscillator)orinstructionclock
WatchdogTimer
Rev.2.1111December29,2008
HT46R23/HT46C23PowerDownOperation-HALT
TheHALTmodeisinitializedbythe²HALT²instructionandresultsinthefollowing...
·ThesystemoscillatorwillbeturnedoffbuttheWDTos-
cillatorkeepsrunning(iftheWDToscillatorisselected).
·ThecontentsoftheonchipRAMandregistersremain
unchanged.
·WDTwillbeclearedandrecountedagain(iftheWDT
set²thatresetsonlytheprogramcounterandstackpointer,leavingtheothercircuitsintheiroriginalstate.Someregistersremainunchangedduringotherresetconditions.Mostregistersareresettothe²initialcondi-tion²whentheresetconditionsaremet.ByexaminingthePDFandTOflags,theprogramcandistinguishbe-tweendifferent²chipresets².TO0u011
PDF0u1u1
RESETConditions
RESresetduringpower-upRESresetduringnormaloperationRESwake-upHALT
WDTtime-outduringnormaloperationWDTwake-upHALT
clockisfromtheWDToscillator).
·AlloftheI/Oportsmaintaintheiroriginalstatus.·ThePDFflagissetandtheTOflagiscleared.
ThesystemcanleavetheHALTmodebymeansofanex-ternalreset,aninterrupt,anexternalfallingedgesignalonportAoraWDToverflow.Anexternalresetcausesade-viceinitializationandtheWDToverflowperformsa²warmreset².AftertheTOandPDFflagsareexamined,therea-sonforchipresetcanbedetermined.ThePDFflagisclearedbysystempower-uporexecutingthe²CLRWDT²instructionandissetwhenexecutingthe²HALT²instruc-tion.TheTOflagissetiftheWDTtime-outoccurs,andcausesawake-upthatonlyresetstheprogramcounterandstackpointer;theotherskeeptheiroriginalstatus.TheportAwake-upandinterruptmethodscanbecon-sideredasacontinuationofnormalexecution.EachbitinportAcanbeindependentlyselectedtowakeupthedevicebytheoptions.AwakeningfromanI/Oportstim-ulus,theprogramwillresumeexecutionofthenextin-struction.Ifitisawakeningfromaninterrupt,twosequencesmayhappen.Iftherelatedinterruptisdis-abledortheinterruptisenabledbutthestackisfull,theprogramwillresumeexecutionatthenextinstruction.Iftheinterruptisenabledandthestackisnotfull,theregu-larinterruptresponsetakesplace.Ifaninterruptrequestflagissetto²1²beforeenteringtheHALTmode,thewake-upfunctionoftherelatedinterruptwillbedisabled.Onceawake-upeventoccurs,ittakes1024tSYS(sys-temclockperiod)toresumenormaloperation.Inotherwords,adummyperiodwillbeinsertedafterwake-up.Ifthewake-upresultsfromaninterruptacknowledgment,theactualinterruptsubroutineexecutionwillbedelayedbyoneormorecycles.Ifthewake-upresultsinthenextinstructionexecution,thiswillbeexecutedimmediatelyafterthedummyperiodisfinished.
Tominimizepowerconsumption,alltheI/OpinsshouldbecarefullymanagedbeforeenteringtheHALTstatus.Reset
Therearethreewaysinwhicharesetcanoccur:
·RESresetduringnormaloperation·RESresetduringHALT
·WDTtime-outresetduringnormaloperation
Note:²u²means²unchanged²
Toguaranteethatthesystemoscillatorisstartedandstabilized,theSST(SystemStart-upTimer)providesanextra-delayof1024systemclockpulseswhenthesys-temreset(power-up,WDTtime-outorRESreset)orthesystemawakesfromtheHALTstate.
ResetTimingChart
ResetCircuit
Note:MostapplicationscanusetheBasicResetCircuitasshown,howeverforapplicationswithextensivenoise,itisrecommendedtousetheHi-noiseResetCircuit.
TheWDTtime-outduringHALTisdifferentfromotherchipresetconditions,sinceitcanperforma²warmre-
ResetConfiguration
12
December29,2008
Rev.2.11
HT46R23/HT46C23Whenasystemresetoccurs,theSSTdelayisaddedduringtheresetperiod.Anywake-upfromHALTwillen-abletheSSTdelay.Thefunctionalunitchipresetstatusareshownbelow.
Anextraoptionloadtimedelayisaddedduringsystemreset(power-up,WDTtime-outatnormalmodeorRESreset).
ProgramCounterInterruptWDT
000HDisable
Clear.Aftermasterreset,WDTbeginscounting
Timer/EventCounterOffInput/OutputPortsStackPointer
Inputmode
Pointstothetopofthestack
Theregistersstatesaresummarizedinthefollowingtable.RegisterTMRLTMRHTMRCProgramCounterMP0MP1ACCTBLPTBLHSTATUSINTC0INTC1PAPACPBPBCPCPCCPDPDCPWM0PWM1HADRHCRHSRHDRADRLADRHADCRACSRNote:
Reset(PowerOn)xxxxxxxxxxxxxxxx00-01000000Hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx-xxxxxxx--00xxxx-0000000---0---011111111111111111111111111111111---11111---11111------11------11xxxxxxxxxxxxxxxxxxxxxxx-0--00---100--0-1xxxxxxxxxx------xxxxxxxx010000001-----00
²*²standsforwarmreset²u²standsforunchanged²x²standsforunknown
WDTTime-outRESReset
(NormalOperation)(NormalOperation)
xxxxxxxxxxxxxxxx00-01000000Huuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuu--1uuuuu-0000000---0---011111111111111111111111111111111---11111---11111------11------11xxxxxxxxxxxxxxxxxxxxxxx-0--00---100--0-1xxxxxxxxxx------xxxxxxxx010000001-----00
xxxxxxxxxxxxxxxx00-01000000Huuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuu--uuuuuu-0000000---0---011111111111111111111111111111111---11111---11111------11------11xxxxxxxxxxxxxxxxxxxxxxx-0--00---100--0-1xxxxxxxxxx------xxxxxxxx010000001-----00
RESReset(HALT)xxxxxxxxxxxxxxxx00-01000000Huuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuu--01uuuu-0000000---0---011111111111111111111111111111111---11111---11111------11------11xxxxxxxxxxxxxxxxxxxxxxx-0--00---100--0-1xxxxxxxxxx------xxxxxxxx010000001-----00
WDTTime-out
(HALT)*uuuuuuuuuuuuuuuuuu-uuuuu000Huuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuu--11uuuu-uuuuuuu---u---uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu---uuuuu---uuuuu------uu------uuuuuuuuuuuuuuuuuuuuuuuuu-u--uu---uuu--u-uuuuuuuuuuuuu----uuuuuuuuuuuuuuuuu-----uu
Rev.2.1113December29,2008
HT46R23/HT46C23Timer/EventCounter
Atimer/eventcounter(TMR)isimplementedinthemicrocontroller.Thetimer/eventcountercontainsan16-bitprogrammablecount-upcounterandtheclockmaycomefromanexternalsourceorthesystemclock.Usingtheinternalsystemclock,thereisonlyonerefer-encetime-base.TheinternalclocksourcecomesfromfSYS.Theexternalclockinputallowstheusertocountexternalevents,measuretimeintervalsorpulsewidths,ortogenerateanaccuratetimebase.
Therearethreeregistersrelatedtothetimer/eventcounter;TMRH(0CH),TMRL(0DH),TMRC(0EH).WritingTMRLwillonlyputthewrittendatatoaninternallower-orderbytebuffer(8bits)andwritingTMRHwilltransferthespecifieddataandthecontentsofthelower-orderbytebuffertoTMRHandTMRLpreloadreg-isters,respectively.Thetimer/eventcounterpreloadregisterischangedbyeachwritingTMRHoperations.ReadingTMRHwilllatchthecontentsofTMRHandTMRLcounterstothedestinationandthelower-orderbytebuffer,respectively.ReadingtheTMRLwillreadthecontentsofthelower-orderbytebuffer.TheTMRCisthetimer/eventcountercontrolregister,whichdefinestheoperatingmode,countingenableordisableandactiveedge.
TheTM0,TM1bitsdefinetheoperatingmode.Theeventcountmodeisusedtocountexternalevents,whichmeanstheclocksourcecomesfromanexternal(TMR)pin.ThetimermodefunctionsasanormaltimerwiththeclocksourcecomingfromthefINTclock.Thepulsewidthmeasurementmodecanbeusedtocountthehighorlowleveldurationoftheexternalsignal(TMR).ThecountingisbasedonthefINT.
Intheeventcountortimermode,oncethetimer/eventcounterstartscounting,itwillcountfromthecurrentcon-tentsinthetimer/eventcountertoFFFFH.Onceoverflowoccurs,thecounterisreloadedfromthetimer/eventcoun-terpreloadregisterandgeneratestheinterruptrequestflag(TF;bit5ofINTC0)atthesametime.InthepulsewidthmeasurementmodewiththeTONandTEbitsequaltoone,oncetheTMRhasreceivedatran-sientfromlowtohigh(orhightolowiftheTEbitsis²0²)itwillstartcountinguntiltheTMRreturnstotheoriginallevelandresetstheTON.Themeasuredresultwillre-maininthetimer/eventcountereveniftheactivatedtransientoccursagain.Inotherwords,onlyonecyclemeasurementcanbedone.UntilsettingtheTON,thecyclemeasurementwillfunctionagainaslongasitre-ceivesfurthertransientpulse.Notethat,inthisoperat-ingmode,thetimer/eventcounterstartscountingnotaccordingtothelogiclevelbutaccordingtothetransientedges.Inthecaseofcounteroverflows,thecounterisreloadedfromthetimer/eventcounterpreloadregisterandissuestheinterruptrequestjustliketheothertwomodes.Toenablethecountingoperation,thetimerONbit(TON;bit4ofTMRC)shouldbesetto1.Inthepulsewidthmeasurementmode,theTONwillbeclearedau-tomaticallyafterthemeasurementcycleiscompleted.ButintheothertwomodestheTONcanonlyberesetbyinstructions.Theoverflowofthetimer/eventcounterisoneofthewake-upsources.Nomatterwhattheopera-tionmodeis,writinga0toETIcandisabletheinterruptservice.
Inthecaseoftimer/eventcounterOFFcondition,writingdatatothetimer/eventcounterpreloadregisterwillalsoreloadthatdatatothetimer/eventcounter.Butifthetimer/eventcounteristurnedon,datawrittentoitwillonlybekeptinthetimer/eventcounterpreloadregister.Thetimer/eventcounterwillstilloperateuntiloverflowoccurs.Whenthetimer/eventcounter(readingTMRH)isread,theclockwillbeblockedtoavoiderrors.Asclockblockingmayresultsinacountingerror,thismustbetakenintoconsiderationbytheprogrammer.Thebit0~bit2oftheTMRCcanbeusedtodefinethepre-scalingstagesoftheinternalclocksourcesofthetimer/eventcounter.Thedefinitionsareasshown.Theoverflowsignalofthetimer/eventcountercanbeusedtogeneratethePFDsignal.Timer/EventCounter
Rev.2.11
14
December29,2008
HT46R23/HT46C23BitNo.
Label
Function
Todefinetheprescalerstages,PSC2,PSC1,PSC0=000:fINT=fSYS001:fINT=fSYS/2010:fINT=fSYS/4011:fINT=fSYS/8100:fINT=fSYS/16101:fINT=fSYS/32110:fINT=fSYS/64111:fINT=fSYS/128
DefinestheTMRactiveedgeofthetimer/eventcounter:InEventCounterMode(TM1,TM0)=(0,1):1:countonfallingedge;0:countonrisingedge
InPulseWidthmeasurementmode(TM1,TM0)=(1,1):
1:startcountingontherisingedge,stoponthefallingedge;0:startcountingonthefallingedge,stopontherisingedgeToenableordisabletimercounting(0=disabled;1=enabled)Unusedbits,readas²0²
Todefinetheoperatingmode
01=Eventcountmode(externalclock)10=Timermode(internalclock)
11=Pulsewidthmeasurementmode00=Unused
TMRC(0EH)Register
Input/OutputPorts
Thereare23bidirectionalinput/outputlinesinthemicrocontroller,labeledasPA,PB,PCandPD,whicharemappedtothedatamemoryof[12H],[14H],[16H]and[18H]respectively.AlloftheseI/Oportscanbeusedforinputandoutputoperations.Forinputopera-tion,theseportsarenon-latching,thatis,theinputsmustbereadyattheT2risingedgeofinstruction²MOVA,[m]²(m=12H,14H,16Hor18H).Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.
EachI/Olinehasitsowncontrolregister(PAC,PBC,PCC,PDC)tocontroltheinput/outputconfiguration.Withthiscontrolregister,CMOSoutputorschmitttrig-gerinputwithorwithoutpull-highresistorstructurescanbereconfigureddynamically(i.e.on-the-fly)undersoft-warecontrol.Tofunctionasaninput,thecorrespondinglatchofthecontrolregistermustwrite²1².Theinputsourcealsodependsonthecontrolregister.Ifthecon-trolregisterbitis²1²,theinputwillreadthepadstate.Ifthecontrolregisterbitis²0²,thecontentsofthelatcheswillmovetotheinternalbus.Thelatterispossibleinthe²read-modify-write²instruction.
Foroutputfunction,CMOSistheonlyconfiguration.Thesecontrolregistersaremappedtolocations13H,15H,17Hand19H.
Afterachipreset,theseinput/outputlinesremainathighlevelsorfloatingstate(dependentonpull-highoptions).Rev.2.11
15
Eachbitoftheseinput/outputlatchescanbesetorclearedby²SET[m].i²and²CLR[m].i²(m=12H,14H,16Hor18H)instructions.
Someinstructionsfirstinputdataandthenfollowtheoutputoperations.Forexample,²SET[m].i²,²CLR[m].i²,²CPL[m]²,²CPLA[m]²readtheentireportstatesintotheCPU,executethedefinedoperations(bit-operation),andthenwritetheresultsbacktothelatchesortheaccumulator.
EachlineofportAhasthecapabilityofwaking-upthedevice.Thehighest3-bitofportCand6-bitofportDarenotphysicallyimplemented;onreadingthema²0²isre-turnedwhereaswritingthenresultsinano-operation.SeeApplicationnote.
EachI/Oporthasapull-highoption.Oncethepull-highoptionisselected,theI/Oporthasapull-highresistor,otherwise,there¢snone.Takenotethatanon-pull-highI/Oportoperatingininputmodewillcauseafloatingstate.
ThePA3ispin-sharedwiththePFDsignal.IfthePFDoptionisselected,theoutputsignalinoutputmodeofPA3willbethePFDsignalgeneratedbythetimer/eventcounteroverflowsignal.Theinputmodealwaysremain-ingitsoriginalfunctions.OncethePFDoptionisse-lected,thePFDoutputsignaliscontrolledbyPA3dataregisteronly.Writing²1²toPA3dataregisterwillenablethePFDoutputfunctionandwriting²0²willforcethe
012PSC0PSC1PSC2
3TE
45
TON¾
67TM0TM1
December29,2008
HT46R23/HT46C23Input/OutputPorts
PA3toremainat²0².TheI/OfunctionsofPA3are
shownbelow.I/OI/PMode(Normal)PA3Note:
LogicalInput
O/P(Normal)LogicalOutput
I/P(PFD)LogicalInput
O/P(PFD)PFD(Timeron)
PD0/PD1.ThePWMchannelshavetheirdataregistersdenotedasPWM0(1AH)andPWM1(1BH).Thefre-quencysourceofthePWMcountercomesfromfSYS.ThePWMregistersaretwo8-bitregisters.Thewave-formsofPWMoutputsareasshown.OncethePD0/PD1areselectedasthePWMoutputsandtheout-putfunctionofPD0/PD1areenabled(PDC.0/PDC.1=²0²),writing²1²toPD0/PD1dataregisterwillenablethePWMoutputfunctionandwriting²0²willforcethePD0/PD1tostayat²0².
A(6+2)bitsmodePWMcycleisdividedintofourmodu-lationcycles(modulationcycle0~modulationcycle3).Eachmodulationcyclehas64PWMinputclockperiod.Ina(6+2)bitPWMfunction,thecontentsofthePWMregisterisdividedintotwogroups.Group1ofthePWMregisterisdenotedbyDCwhichisthevalueofPWM.7~PWM.2.Thegroup2isdenotedbyACwhichisthevalueofPWM.1~PWM.0.
Ina(6+2)bitsmodePWMcycle,thedutycycleofeachmodulationcycleisshowninthetable.
ParameterModulationcyclei(i=0~3)AC(0~3)i ThePBcanalsobeusedasA/Dconverterinputs.TheA/Dfunctionwillbedescribedlater.ThereisaPWMfunctionsharedwithPD0/PD1.IfthePWMfunctionisenabled,thePWM0/PWM1signalwillappearonPD0/PD1(ifPD0/PD1isoperatinginoutputmode).Writing²1²toPD0/PD1dataregisterwillenablethePWM0/PWM1outputfunctionandwriting²0²willforcethePD0/PD1toremainat²0².TheI/OfunctionsofPD0/PD1areasshown.I/OI/PMode(Normal)PD0PD1 LogicalInput O/P(Normal)LogicalOutput I/P(PWM)LogicalInput O/P(PWM)PWM0PWM1 ItisrecommendedthatunusedornotbondedoutI/Olinesshouldbesetasoutputpinsbysoftwareinstructiontoavoidconsumingpowerunderinputfloatingstate.PWM Themicrocontrollerprovides2channels(6+2)/(7+1)(dependentonoptions)bitsPWMoutputsharedwithRev.2.11 16 A(7+1)bitsmodePWMcycleisdividedintotwomodu-lationcycles(modulationcycle0~modulationcycle1).Eachmodulationcyclehas128PWMinputclockperiod.Ina(7+1)bitsPWMfunction,thecontentsofthePWMregisterisdividedintotwogroups.Group1ofthePWMregisterisdenotedbyDCwhichisthevalueof December29,2008 HT46R23/HT46C23(6+2)PWMMode (7+1)PWMMode PWM.7~PWM.1.Thegroup2isdenotedbyACwhichisthevalueofPWM.0. Ina(7+1)bitsmodePWMcycle,thedutycycleofeachmodulationcycleisshowninthetable. ParameterModulationcyclei(i=0~1)AC(0~1)i Themodulationfrequency,cyclefrequencyandcycledutyofthePWMoutputsignalaresummarizedinthefollowingtable. PWM ModulationFrequencyfSYS/64for(6+2)bitsmodefSYS/128for(7+1)bitsmode PWMCyclePWMCycleFrequencyDutyfSYS/256 [PWM]/256 Rev.2.1117December29,2008 HT46R23/HT46C23TheA/DconvertercontrolregisterisusedtocontroltheA/Dconverter.Thebit2~bit0oftheADCRareusedtoselectananaloginputchannel.Thereareatotalofeightchannelstoselect.Thebit5~bit3oftheADCRareusedtosetPBconfigurations.PBcanbeananaloginputorasdigitalI/Olinedecidedbythese3bits.OnceaPBlineisselectedasananaloginput,theI/Ofunctionsandpull-highresistorofthisI/OlinearedisabledandtheA/Dconvertercircuitispoweron.TheEOCBbit(bit6oftheADCR)isendofA/Dconversionflag.CheckthisbittoknowwhenA/Dconversioniscompleted.TheSTARTbitoftheADCRisusedtobegintheconversionoftheA/Dconverter.GivingSTARTbitarisingedgeandfall-ingedgemeansthattheA/Dconversionhasstarted.InordertoensuretheA/Dconversioniscompleted,theBitNo.01234567 LabelACS0ACS1ACS2PCR0PCR1PCR2EOCB Definestheanalogchannelselect. STARTshouldremainat²0²untiltheEOCBisclearedto²0²(endofA/Dconversion).BitNo. Label Function SelectstheA/Dconverterclocksource 00=systemclock/201=systemclock/810=systemclock/3211=undefinedUnusedbit,readas²0²Fortestmodeusedonly 01ADCS0ADCS1 2~67 ¾TEST ACSR(27H)Register Function DefinestheportBconfigurationselect.IfPCR0,PCR1andPCR2areallzero,theADCcircuitispowerofftoreducepowerconsumption IndicatesendofA/Dconversion.(0=endofA/Dconversion) Eachtimebits3~5changestatetheA/DshouldbeinitializedbyissuingaSTARTsignal,other-wisetheEOCBflagmayhaveanundefinedcondition.See²ImportantnoteforA/Dinitialization². STARTStartstheA/Dconversion.(0®1®0=start;0®1=ResetA/DconverterandsetEOCBto²1²) ADCR(26H)Register PCR200001111 PCR100110011 PCR001010101 7PB7PB7PB7PB7PB7PB7PB7AN7 6PB6PB6PB6PB6PB6PB6PB6AN6 5PB5PB5PB5PB5PB5PB5AN5AN5 4PB4PB4PB4PB4PB4AN4AN4AN4 3PB3PB3PB3PB3AN3AN3AN3AN3 2PB2PB2PB2AN2AN2AN2AN2AN2 1PB1PB1AN1AN1AN1AN1AN1AN1 0PB0AN0AN0AN0AN0AN0AN0AN0 PortBConfiguration ACS200001111 ACS100110011 ACS001010101 AnalogInputChannelSelection Rev.2.11 18 December29,2008 AnalogChannel AN0AN1AN2AN3AN4AN5AN6AN7 HT46R23/HT46C23Bit7oftheACSRregisterisusedfortestpurposesonlyandmustnotbeusedforotherpurposesbytheapplica-tionprogram.Bit1andbit0oftheACSRregisterareusedtoselecttheA/Dclocksource. WhentheA/Dconversionhascompleted,theA/Dinter-ruptrequestflagwillbeset.TheEOCBbitissetto²1²whentheSTARTbitissetfrom²0²to²1². ImportantNoteforA/Dinitialization: SpecialcaremustbetakentoinitializetheA/Dcon-vertereachtimethePortBA/Dchannelselectionbitsaremodified,otherwisetheEOCBflagmaybeinanun-definedcondition.AnA/Dinitializationisimplemented bysettingtheSTARTbithighandthenclearingittozerowithin10instructioncyclesofthePortBchannelselec-tionbitsbeingmodified.NotethatifthePortBchannelselectionbitsareallclearedtozerothenanA/Dinitial-izationisnotrequired. RegisterBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0ADRLADRHNote: D1D9 D0D8 ¾D7 ¾D6 ¾D5 ¾D4 ¾D3 ¾D2 D0~D9isA/DconversionresultdatabitLSB~MSB. ADRL(24H),ADRH(25H)Register ThefollowingtwoprogrammingexamplesillustratehowtosetupandimplementanA/Dconversion.Inthefirstexam-ple,themethodofpollingtheEOCBbitintheADCRregisterisusedtodetectwhentheconversioncycleiscomplete,whereasinthesecondexample,theA/Dinterruptisusedtodeterminewhentheconversioniscomplete.Example:usingEOCBPollingMethodtodetectendofconversion clrmovmovmovmov EADIa,00000001BACSR,a a,00100000BADCR,a::: Start_conversion: clrsetclrszjmpmovmovmovmov STARTSTARTSTARTEOCBpolling_EOCa,ADRHadrh_buffer,aa,ADRLadrl_buffer,a:: jmp start_conversion ;startnextA/Dconversion;resetA/D;startA/D ;polltheADCRregisterEOCBbittodetectendofA/Dconversion;continuepolling ;readconversionresulthighbytevaluefromtheADRHregister;saveresulttouserdefinedmemory ;readconversionresultlowbytevaluefromtheADRLregister;saveresulttouserdefinedmemory ;AsthePortBchannelbitshavechangedthefollowingSTART;signal(0-1-0)mustbeissuedwithin10instructioncycles;setuptheACSRregistertoselectfSYS/8astheA/Dclock ;setupADCRregistertoconfigurePortPB0~PB3asA/Dinputs;andselectAN0tobeconnectedtotheA/Dconverter;disableADCinterrupt Polling_EOC: Example:usinginterruptmethodtodetectendofconversion clrmovmovmovmov EADIa,00000001BACSR,aa,00100000BADCR,a: ;AsthePortBchannelbitshavechangedthefollowingSTART;signal(0-1-0)mustbeissuedwithin10instructioncycles : ;setuptheACSRregistertoselectfSYS/8astheA/Dclock;setupADCRregistertoconfigurePortPB0~PB3asA/Dinputs;andselectAN0tobeconnectedtotheA/Dconverter;disableADCinterrupt Rev.2.1119December29,2008 HT46R23/HT46C23Start_conversion: clrsetclrclrsetset STARTSTARTSTARTADFEADIEMI::: ;ADCinterruptserviceroutineADC_ISR: movmovmov acc_stack,aa,STATUSstatus_stack,a:: movmovmovmovclrsetclr a,ADRHadrh_buffer,aa,ADRLadrl_buffer,aSTARTSTARTSTART:: EXIT_INT_ISR: movmovmovreti a,status_stackSTATUS,aa,acc_stack ;restoreSTATUSfromuserdefinedmemory;restoreACCfromuserdefinedmemory;resetA/D;startA/D ;readconversionresulthighbytevaluefromtheADRHregister;saveresulttouserdefinedregister ;readconversionresultlowbytevaluefromtheADRLregister;saveresulttouserdefinedregister;saveSTATUStouserdefinedmemory;saveACCtouserdefinedmemory;resetA/D;startA/D ;clearADCinterruptrequestflag;enableADCinterrupt;enableglobalinterrupt A/DConversionTiming Rev.2.1120December29,2008 HT46R23/HT46C23LowVoltageReset-LVR Themicrocontrollerprovideslowvoltageresetcircuitinordertomonitorthesupplyvoltageofthedevice.Ifthesupplyvoltageofthedeviceiswithintherange0.9V~3.3V,suchaschangingabattery,theLVRwillau-tomaticallyresetthedeviceinternally.TheLVRincludesthefollowingspecifications: ·Thelowvoltage(0.9V~VLVR)hastoremainintheir I2CBusSerialInterface I2CBusisimplementedinthedevice.TheI2CBusisabidirectionaltwo-wirelines.ThedatalineandclocklineareimplementinSDApinandSCLpin.TheSDAandSCLareNMOSopendrainoutputpin.Theymustcon-nectapull-highresistorrespectively. UsingtheI2CBus,thedevicehastwowaystotransferdata.Oneisinslavetransmitmode,theotherisinslavereceivemode.TherearefourregistersrelatedtoI2CBus;HADR([20H]),HCR([21H]),HSR([22H]),HDR([23H]).TheHADRregisteristheslaveaddresssettingofthedevice,ifthemastersendsthecallingad-dresswhichmatch,itmeansthatthisdeviceisselected.TheHCRisI2CBuscontrolregisterwhichdefinesthedeviceenableordisabletheI2CBusasatransmitterorasareceiver.TheHSRisI2CBusstatusregister,itre-spondswiththeI2CBusstatus.TheHDRisinput/outputdataregister,datatotransmitorreceivemustbeviatheHDRregister. TheI2CBuscontrolregistercontainsthreebits.TheHENbitdefinetheenableordisabletheI2CBus.IfthedatawantstransferviaI2CBus,thisbitmustbeset.TheHTXbitdefineswhethertheI2CBusisintransmitorre-ceivemode.Ifthedeviceisasatransmitter,thisbitmustbesetto²1².TheTXAKdefinesthetransmitacknowl-edgesignal,whenthedevicereceived8-bitdata,thedevicesendsthisbittoI2CBusatthe9thclock.Ifthere-ceiverwantstocontinuetoreceivethenextdata,thisbitmustberesetto²0²beforereceivingdata. originalstatetoexceed1ms.Ifthelowvoltagestatedoesnotexceed1ms,theLVRwillignoreitanddonotperformaresetfunction. ·TheLVRusesthe²OR²functionwiththeexternalRESsignaltoperformchipreset. TherelationshipbetweenVDDandVLVRisshownbelow. Note:VOPRisthevoltagerangeforproperchip operationat4MHzsystemclock. LowVoltageReset Note: *1:Tomakesurethatthesystemoscillatorhasstabilized,theSSTprovidesanextradelayof1024system clockpulsesbeforeenteringthenormaloperation.*2:Sincelowvoltagestatehastobemaintainedinitsoriginalstateforover1ms,thereforeafter1msdelay, thedeviceenterstheresetmode. Rev.2.1121December29,2008 HT46R23/HT46C23TheI2CBusstatusregistercontains5bits.TheHCFbitisresetto²0²whenonedatabyteisbeingtransferred.Ifonedatatransferiscompleted,thisbitissetto²1².TheHASSbitisset²1²whentheaddressismatch,andtheI2CBusinterruptrequestflagissetto²1².Iftheinterruptisenabledandthestackisnotfull,asubroutinecalltolocation10Hwilloccur.WritingdatatotheI2CBuscon-trolregisterclearsHAASbit.Iftheaddressisnotmatch,thisbitisresetto²0².TheHBBbitissettorespondtheI2CBusisbusy.ItmeanthataSTARTsignalisdetected.Thisbitisresetto²0²whentheI2CBusisnotbusy.ItmeansthataSTOPsignalisdetectedandtheI2CBusisfree.TheSRWbitdefinestheread/writecommandbit,ifthecallingaddressismatch.WhenHAASissetto²1²,thedevicecheckSRWbittodeterminewhetherthede-viceisworkingintransmitorreceivemode.WhenSRWbitisset²1²,itmeansthatthemasterwantstoreaddatafromI2CBus,theslavedevicemustwritedatatoI2CBus,sotheslavedeviceisworkingintransmitmode.WhenSRWisresetto²0²,itmeansthatthemasterwantstowritedatatoI2CBus,theslavedevicemustreaddatafromthebus,sotheslavedeviceisworkinginreceivemode.TheRXAKbitisreset²0²indicatesanac-knowledgessignalhasbeenreceived.Inthetransmitmode,thetransmitterchecksRXAKbittoknowthere-ceiverwhichwantstoreceivethenextdatabyte,sothetransmittercontinuetowritedatatotheI2CBusuntiltheRXAKbitissetto²1²andthetransmitterreleasestheSDAline,sothatthemastercansendtheSTOPsignaltoreleasethebus. TheHADRbit7-bit1definethedeviceslaveaddress.Atthebeginningoftransfer,themastermustselectade-vicebysendingtheaddressoftheslavedevice.Thebit0isunusedandisnotdefined.IftheI2CBusreceivesastartsignal,allslavedevicenoticethecontinuityofthe8-bitdata.Thefrontof7bitsisslaveaddressandthefirstbitisMSB.Iftheaddressismatch,theHAASstatusbitissetandgenerateanI2CBusinterrupt.IntheISR,theslavedevicemustchecktheHAASbittoknowtheI2CBusinterruptcomesfromtheslaveaddressthathasmatchorcompletedone8-bitdatatransfer.Thelastbitofthe8-bitdataisread/writecommandbit,itrespondsinSRWbit.TheslavewillchecktheSRWbittoknowifthemasterwantstotransmitorreceivedata.ThedevicecheckSRWbittoknowitisasatransmitterorreceiver. Bit7~Bit1 SlaveAddress ²¾²meansundefined HADR(20H)Register TheHDRregisteristheI2CBusinput/outputdataregis-ter.Beforetransmittingdata,theHDRmustwritethedatawhichwewanttotransmit.Beforereceivingdata,thedevicemustdummyreaddatafromHDR.TransmitorReceivedatafromI2CBusmustbeviatheHDRreg-Rev.2.11 22 7 Bit0¾ 6 ister.AtthebeginningofthetransferoftheI2CBus,thedevicemustinitialthebus,thefollowingarethenotesforinitialingtheI2CBus.Note: 1.WritetheI2CBusaddressregister(HADR)todefineitsownslaveaddress. 2.SetHENbitofI2CBuscontrolregister(HCR)bit0toenabletheI2CBus.BitNo.2~03 Label¾ Function Unusedbit,readas²0² Toenableordisabletransmitac-TXAKknowledge(0=acknowledge;1=don¢t acknowledge)HTX¾HEN Todefinethetransmit/receivemode(0=receivemode;1=transmit)Unusedbit,readas²0² ToenableordisableI2CBusfunction(0=disable;1=enable)HCR(21H)Register 45~67 3.SetEHIbitoftheinterruptcontrolregister1(INTC1)bit0toenabletheI2CBusinterrupt.BitNo. Label Function 0 RXAKisclearedto²0²whenthemasterreceivesan8-bitdataandac-RXAKknowledgmentatthe9thclock, RXAKissetto²1²meansnotac-knowledged.¾ Unusedbit,readas²0² SRWissetto²1²whenthemasterwantstoreaddatafromtheI2CBus,sotheslavemusttransmitdatatothemaster.SRWisclearedto²0²whenthemasterwantstowritedatatotheI2CBus,sotheslavemustreceivedatafromthemaster.Unusedbit,readas²0² HBBissetto²1²whenI2CBusisbusyandHBBisclearedto²0²meansthattheI2CBusisnotbusy. 1 2SRW 3~45 ¾HBB HAASissetto²1²whenthecalling HAASaddresshasmatched,andI2CBus interruptwilloccurandHIFisset. HCFisclearto²0²whenonedatabyteisbeingtransferred,HCFissetto²1²indicating8-bitdatacommuni-cationhasbeenfinished.HSR(22H)Register HCF December29,2008 HT46R23/HT46C23Rev.2.1123December29,2008 HT46R23/HT46C23I2CCommunicationTimingDiagram StartSignal TheSTARTsignalisgeneratedonlybythemasterde-vice.TheotherdeviceinthebusmustdetecttheSTARTsignaltosettheI2CBusbusybit(HBB).TheSTARTsig-nalisSDAlinefromhightolow,whenSCLishigh. Ininterruptsubroutine,checkHAASbittoknowwhethertheI2CBusinterruptcomesfromaslaveaddressthatismatchedoradatabytetransferiscompleted.Whentheslaveaddressismatched,thedevicemustbeintrans-mitmodeorreceivemodeandwritedatatoHDRordummyreadfromHDRtoreleasetheSCLline.SRWBit TheSRWbitmeansthatthemasterdevicewantstoreadfromorwritetotheI2CBus.Theslavedevicecheckthisbittounderstanditselfifitisatransmitterorareceiver.TheSRWbitissetto²1²meansthatthemas-terwantstoreaddatafromtheI2CBus,sotheslavede-vicemustwritedatatoabusasatransmitter.TheSRWisclearedto²0²meansthatthemasterwantstowritedatatotheI2CBus,sotheslavedevicemustreaddatafromtheI2CBusasareceiver. StartBit SlaveAddress ThemastermustselectadevicefortransferringthedatabysendingtheslavedeviceaddressaftertheSTARTsignal.AlldeviceintheI2CBuswillreceivetheI2CBusslaveaddress(7bits)tocomparewithitsownslaveaddress(7bits).Iftheslaveaddressismatched,theslavedevicewillgenerateaninterruptandsavethefollowingbit(8thbit)toSRWbitandsendsanacknowl-edgebit(lowlevel)tothe9thbit.Theslavedevicealsosetsthestatusflag(HAAS),whentheslaveaddressismatched. Rev.2.1124December29,2008 HT46R23/HT46C23AcknowledgeBit Oneoftheslavedevicegeneratesanacknowledgesignal,whentheslaveaddressismatched.Themasterdevicecancheckthisacknowledgebittoknowiftheslavedeviceacceptsthecallingaddress.Ifnoacknowledgebit,themastermustsendaSTOPbitandendthecommunication.WhentheI2CBusstatusregisterbit6HAASishigh,itmeanstheaddressismatched,sotheslavemustcheckSRWasatransmitter(setHTX)to²1²orasareceiver(clearHTX)to²0². bytedata.Ifthetransmitterchecksandthere¢snoac-knowledgesignal,thenitreleasetheSDAline,andthemastersendsaSTOPsignaltoreleasetheI2CBus.ThedataisstoredintheHDRregister.ThetransmittermustwritedatatotheHDRbeforetransmitdataandthere-ceivermustreaddatafromtheHDRafterreceivingdata. DataTimingDiagram StopBit ReceiveAcknowledgeBit Whenthereceiverwantstocontinuetoreceivethenextdatabyte,itgeneratesanacknowledgebit(TXAK)atthe9thclock.Thetransmittercheckstheacknowledgebit(RXAK)tocontinuetowritedatatotheI2CBusorchangetoreceivemodeanddummyreadtheHDRreg-istertoreleasetheSDAlineandthemastersendstheSTOPsignal. DataByte Thedatais8bitsandissentaftertheslavedevicehasacknowledgestheslaveaddress.ThefirstbitisMSBandthe8thbitisLSB.Thereceiversendstheacknowl-edgesignal(²0²)andcontinuestoreceivethenextone Options Thefollowingtableshowsallkindsofoptionsinthemicrocontroller.Alloftheoptionsmustbedefinedtoensurepropersystemfunction.No.12 Options OSCtypeselection. ThisoptionistodecideifanRCorcrystaloscillatorischosenassystemclock. WDTsourceselection. Therearethreetypesofselection:on-chipRCoscillator,instructionclockordisabletheWDT. CLRWDTtimesselection. ThisoptiondefineshowtocleartheWDTbyinstruction.²Onetime²meansthattheCLRWDTinstructioncancleartheWDT.²Twotimes²meansonlyifbothoftheCLRWDT1andCLRWDT2instructionshavebeenexe-cuted,thenWDTcanbecleared. Wake-upselection. Thisoptiondefinesthewake-upfunctionactivity.ExternalI/Opins(PAonly)allhavethecapabilitytowake-upthechipfromaHALT. Pull-highselection. Thisoptionistodecidewhetherapull-highresistanceisvisibleornotintheinputmodeoftheI/Oports.PA0~PA7,canbeindependentlyselected.PFDselection. PA3:leveloutputorPFDoutputPWMselection:(7+1)or(6+2)modePD0:leveloutputorPWM0outputPD1:leveloutputorPWM1output WDTtime-outperiodselection. 212/fS~213/fS,213/fS~214/fS,214/fS~215/fS,215/fS~216/fS.Lowvoltageresetselection:EnableordisableLVRfunction.I2CBusselection. PA6andPA7:I/OorI2CBusfunction 3 4 5 6 7 8910 Rev.2.1125December29,2008 HT46R23/HT46C23ApplicationCircuits Note:1.Crystal/resonatorsystemoscillators Forcrystaloscillators,C1andC2areonlyrequiredforsomecrystalfrequenciestoensureoscillation.ForresonatorapplicationsC1andC2arenormallyrequiredforoscillationtooccur.FormostapplicationsitisnotnecessarytoaddR1.HoweveriftheLVRfunctionisdisabled,andifitisrequiredtostoptheoscillatorwhenVDDfallsbelowitsoperatingrange,itisrecommendedthatR1isadded.ThevaluesofC1andC2shouldbeselectedinconsultationwiththecrystal/resonatormanufacturerspecifications.2.Resetcircuit TheresetcircuitresistanceandcapacitancevaluesshouldbechosentoensurethatVDDisstableandre-mainswithinitsoperatingvoltagerangebeforetheRESpinreachesahighlevel.EnsurethatthelengthofthewiringconnectedtotheRESpiniskeptasshortaspossible,toavoidnoiseinterference. 3.Forapplicationswherenoisemayinterferewiththeresetcircuitandfordetailsontheoscillatorexternalcomponents,refertoApplicationNoteHA0075Eformoreinformation. Rev.2.1126December29,2008 HT46R23/HT46C23InstructionSet Introduction Centraltothesuccessfuloperationofanymicrocontrollerisitsinstructionset,whichisasetofpro-graminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontrollers,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofpro-grammingoverheads. Foreasierunderstandingofthevariousinstructioncodes,theyhavebeensubdividedintoseveralfunc-tionalgroupings.InstructionTiming Mostinstructionsareimplementedwithinoneinstruc-tioncycle.Theexceptionstothisarebranch,call,orta-blereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5msandbranchorcallinstructionswouldbeim-plementedwithin1ms.Althoughinstructionswhichre-quireonemorecycletoimplementaregenerallylimitedtotheJMP,CALL,RET,RETIandtablereadinstruc-tions,itisimportanttorealizethatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimple-ment.AsinstructionswhichchangethecontentsofthePCLwillimplyadirectjumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstruc-tionswouldbe²CLRPCL²or²MOVPCL,A².Forthecaseofskipinstructions,itmustbenotedthatifthere-sultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.MovingandTransferringData Thetransferofdatawithinthemicrocontrollerprogramisoneofthemostfrequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimme-diatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsistoreceivedatafromtheinputportsandtransferdatatotheoutputports.ArithmeticOperations Theabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddand subtractinstructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbetakentoen-surecorrecthandlingofcarryandborrowdatawhenre-sultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.LogicalandRotateOperations ThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontrollerinstructionset.Aswiththecaseofmostinstructionsinvolvingdatamanipulation,datamustpassthroughtheAccumulatorwhichmayinvolveadditionalprogrammingsteps.Inalllogicaldataoperations,thezeroflagmaybesetiftheresultoftheoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonpro-gramrequirements.RotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregisterintotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhererotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations. BranchesandControlTransfer ProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionortoasub-routineusingtheCALLinstruction.Theydifferinthesensethatinthecaseofasubroutinecall,theprogrammustreturntotheinstructionimmediatelywhenthesub-routinehasbeencarriedout.ThisisdonebyplacingareturninstructionRETinthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmadere-gardingtheconditionofacertaindatamemoryorindi-vidualbits.Dependingupontheconditions,theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.Theseinstructionsarethekeytodecisionmakingandbranchingwithinthepro-gramperhapsdeterminedbytheconditionofcertainin-putswitchesorbytheconditionofinternaldatabits. Rev.2.1127December29,2008 HT46R23/HT46C23BitOperations TheabilitytoprovidesinglebitoperationsonDataMem-oryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeatureisespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe²SET[m].i²or²CLR[m].i²instructionsrespectively.Thefea-tureremovestheneedforprogrammerstofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writepro-cessistakencareofautomaticallywhenthesebitoper-ationinstructionsareused.TableReadOperations Datastorageisnormallyimplementedbyusingregis-ters.However,whenworkingwithlargeamountsoffixeddata,thevolumeinvolvedoftenmakesitinconve-nienttostorethefixeddataintheDataMemory.Toover-comethisproblem,HoltekmicrocontrollersallowanareaofProgramMemorytobesetupasatablewheredatacanbedirectlystored.Asetofeasytouseinstruc-tionsprovidesthemeansbywhichthisfixeddatacanbereferencedandretrievedfromtheProgramMemory. OtherOperations Inadditiontotheabovefunctionalinstructions,arangeofotherinstructionsalsoexistsuchasthe²HALT²in-structionforPower-downoperationsandinstructionstocontroltheoperationoftheWatchdogTimerforreliableprogramoperationsunderextremeelectricorelectro-magneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.InstructionSetSummary Thefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbecon-sultedasabasicinstructionreferenceusingthefollow-inglistedconventions.Tableconventions:x:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbits addr:Programmemoryaddress MnemonicArithmeticADDA,[m]ADDMA,[m]ADDA,xADCA,[m]ADCMA,[m]SUBA,xSUBA,[m]SUBMA,[m]SBCA,[m]SBCMA,[m]DAA[m]ANDA,[m]ORA,[m]XORA,[m]ANDMA,[m]ORMA,[m]XORMA,[m]ANDA,xORA,xXORA,xCPL[m]CPLA[m]INCA[m]INC[m]DECA[m]DEC[m] Description AddDataMemorytoACCAddACCtoDataMemoryAddimmediatedatatoACC AddDataMemorytoACCwithCarryAddACCtoDatamemorywithCarrySubtractimmediatedatafromtheACCSubtractDataMemoryfromACC SubtractDataMemoryfromACCwithresultinDataMemorySubtractDataMemoryfromACCwithCarry SubtractDataMemoryfromACCwithCarry,resultinDataMemoryDecimaladjustACCforAdditionwithresultinDataMemoryLogicalANDDataMemorytoACCLogicalORDataMemorytoACCLogicalXORDataMemorytoACCLogicalANDACCtoDataMemoryLogicalORACCtoDataMemoryLogicalXORACCtoDataMemoryLogicalANDimmediateDatatoACCLogicalORimmediateDatatoACCLogicalXORimmediateDatatoACCComplementDataMemory ComplementDataMemorywithresultinACCIncrementDataMemorywithresultinACCIncrementDataMemory DecrementDataMemorywithresultinACCDecrementDataMemory Cycles11Note11Note111Note111Note1Note111 FlagAffectedZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OV C ZZZZZZZZZZZZZZZ LogicOperation 1Note1Note1Note111Note111 Increment&Decrement 1 Note 11Note Rev.2.1128December29,2008 HT46R23/HT46C23MnemonicRotateRRA[m]RR[m]RRCA[m]RRC[m]RLA[m]RL[m]RLCA[m]RLC[m]DataMoveMOVA,[m]MOV[m],AMOVA,xBitOperationCLR[m].iSET[m].iBranchJMPaddrSZ[m]SZA[m]SZ[m].iSNZ[m].iSIZ[m]SDZ[m]SIZA[m]SDZA[m]CALLaddrRETRETA,xRETITableReadTABRDC[m]TABRDL[m]MiscellaneousNOPCLR[m]SET[m]CLRWDTCLRWDT1CLRWDT2SWAP[m]SWAPA[m]HALTNote: Nooperation ClearDataMemorySetDataMemory ClearWatchdogTimerPre-clearWatchdogTimerPre-clearWatchdogTimerSwapnibblesofDataMemory SwapnibblesofDataMemorywithresultinACCEnterpowerdownmode 11Note1Note111Note111 NoneNoneNoneTO,PDFTO,PDFTO,PDFNoneNoneTO,PDF Readtable(currentpage)toTBLHandDataMemoryReadtable(lastpage)toTBLHandDataMemory 2Note2Note NoneNone Jumpunconditionally SkipifDataMemoryiszero SkipifDataMemoryiszerowithdatamovementtoACCSkipifbitiofDataMemoryiszeroSkipifbitiofDataMemoryisnotzeroSkipifincrementDataMemoryiszeroSkipifdecrementDataMemoryiszero SkipifincrementDataMemoryiszerowithresultinACCSkipifdecrementDataMemoryiszerowithresultinACCSubroutinecall Returnfromsubroutine ReturnfromsubroutineandloadimmediatedatatoACCReturnfrominterrupt 11note1Note1Note1Note1Note1Note1Note2222 Note Description RotateDataMemoryrightwithresultinACCRotateDataMemoryright RotateDataMemoryrightthroughCarrywithresultinACCRotateDataMemoryrightthroughCarryRotateDataMemoryleftwithresultinACCRotateDataMemoryleft RotateDataMemoryleftthroughCarrywithresultinACCRotateDataMemoryleftthroughCarryMoveDataMemorytoACCMoveACCtoDataMemoryMoveimmediatedatatoACCClearbitofDataMemorySetbitofDataMemory Cycles1 FlagAffected NoneNoneCCNoneNoneCCNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNone 1111 NoteNoteNoteNote 111 1 Note 1 11Note1Note2 1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired. 2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.Forthe²CLRWDT1²and²CLRWDT2²instructionstheTOandPDFflagsmaybeaffectedbytheexecutionstatus.TheTOandPDFflagsareclearedafterboth²CLRWDT1²and²CLRWDT2²instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged. Rev.2.1129December29,2008 HT46R23/HT46C23InstructionDefinition ADCA,[m]DescriptionOperationAffectedflag(s)ADCMA,[m]DescriptionOperationAffectedflag(s)ADDA,[m]DescriptionOperationAffectedflag(s)ADDA,xDescriptionOperationAffectedflag(s)ADDMA,[m]DescriptionOperationAffectedflag(s)ANDA,[m]DescriptionOperationAffectedflag(s)ANDA,xDescriptionOperationAffectedflag(s)ANDMA,[m]DescriptionOperationAffectedflag(s)Rev.2.11 AddDataMemorytoACCwithCarry ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded.TheresultisstoredintheAccumulator.ACC¬ACC+[m]+COV,Z,AC,C AddACCtoDataMemorywithCarry ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded.TheresultisstoredinthespecifiedDataMemory.[m]¬ACC+[m]+COV,Z,AC,C AddDataMemorytoACC ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded.TheresultisstoredintheAccumulator.ACC¬ACC+[m]OV,Z,AC,C AddimmediatedatatoACC ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded.TheresultisstoredintheAccumulator.ACC¬ACC+xOV,Z,AC,C AddACCtoDataMemory ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded.TheresultisstoredinthespecifiedDataMemory.[m]¬ACC+[m]OV,Z,AC,C LogicalANDDataMemorytoACC DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalANDop-eration.TheresultisstoredintheAccumulator.ACC¬ACC²AND²[m]Z LogicalANDimmediatedatatoACC DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalANDoperation.TheresultisstoredintheAccumulator.ACC¬ACC²AND²xZ LogicalANDACCtoDataMemory DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalANDop-eration.TheresultisstoredintheDataMemory.[m]¬ACC²AND²[m]Z 30 December29,2008 HT46R23/HT46C23CALLaddrDescription Subroutinecall Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthenin-crementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothestack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthisnewaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruc-tion. Stack¬ProgramCounter+1ProgramCounter¬addrNone ClearDataMemory EachbitofthespecifiedDataMemoryisclearedto0.[m]¬00HNone ClearbitofDataMemory BitiofthespecifiedDataMemoryisclearedto0.[m].i¬0None ClearWatchdogTimer TheTO,PDFflagsandtheWDTareallcleared.WDTclearedTO¬0PDF¬0TO,PDF Pre-clearWatchdogTimer TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunc-tionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohaveeffect.Re-petitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2willhavenoeffect.WDTclearedTO¬0PDF¬0TO,PDF Pre-clearWatchdogTimer TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunc-tionwithCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect.Re-petitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhavenoeffect.WDTclearedTO¬0PDF¬0TO,PDF OperationAffectedflag(s)CLR[m]DescriptionOperationAffectedflag(s)CLR[m].iDescriptionOperationAffectedflag(s)CLRWDTDescriptionOperation Affectedflag(s)CLRWDT1Description Operation Affectedflag(s)CLRWDT2Description Operation Affectedflag(s) Rev.2.1131December29,2008 HT46R23/HT46C23CPL[m]DescriptionOperationAffectedflag(s)CPLA[m]Description ComplementDataMemory EachbitofthespecifiedDataMemoryislogicallycomplemented(1¢scomplement).Bitswhichpreviouslycontaineda1arechangedto0andviceversa.[m]¬[m]Z ComplementDataMemorywithresultinACC EachbitofthespecifiedDataMemoryislogicallycomplemented(1¢scomplement).Bitswhichpreviouslycontaineda1arechangedto0andviceversa.ThecomplementedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremainunchanged.ACC¬[m]Z Decimal-AdjustACCforadditionwithresultinDataMemory ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)valuere-sultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibbleremainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadd-ing00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflagmaybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan100,itallowsmultipleprecisiondecimaladdition.[m]¬ACC+00Hor[m]¬ACC+06Hor[m]¬ACC+60Hor[m]¬ACC+66HC DecrementDataMemory DatainthespecifiedDataMemoryisdecrementedby1.[m]¬[m]-1Z DecrementDataMemorywithresultinACC DatainthespecifiedDataMemoryisdecrementedby1.TheresultisstoredintheAccu-mulator.ThecontentsoftheDataMemoryremainunchanged.ACC¬[m]-1Z Enterpowerdownmode Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.ThecontentsoftheDataMemoryandregistersareretained.TheWDTandprescalerarecleared.ThepowerdownflagPDFissetandtheWDTtime-outflagTOiscleared.TO¬0PDF¬1TO,PDF OperationAffectedflag(s)DAA[m]Description Operation Affectedflag(s)DEC[m]DescriptionOperationAffectedflag(s)DECA[m]DescriptionOperationAffectedflag(s)HALTDescription OperationAffectedflag(s) Rev.2.1132December29,2008 HT46R23/HT46C23INC[m]DescriptionOperationAffectedflag(s)INCA[m]DescriptionOperationAffectedflag(s)JMPaddrDescription IncrementDataMemory DatainthespecifiedDataMemoryisincrementedby1.[m]¬[m]+1Z IncrementDataMemorywithresultinACC DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumu-lator.ThecontentsoftheDataMemoryremainunchanged.ACC¬[m]+1Z Jumpunconditionally ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Programexecutionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummyinstructionwhilethenewaddressisloaded,itisatwocycleinstruction.ProgramCounter¬addrNone MoveDataMemorytoACC ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.ACC¬[m]None MoveimmediatedatatoACC TheimmediatedataspecifiedisloadedintotheAccumulator.ACC¬xNone MoveACCtoDataMemory ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.[m]¬ACCNoneNooperation Nooperationisperformed.Executioncontinueswiththenextinstruction.NooperationNone LogicalORDataMemorytoACC DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalORoper-ation.TheresultisstoredintheAccumulator.ACC¬ACC²OR²[m]Z OperationAffectedflag(s)MOVA,[m]DescriptionOperationAffectedflag(s)MOVA,xDescriptionOperationAffectedflag(s)MOV[m],ADescriptionOperationAffectedflag(s)NOPDescriptionOperationAffectedflag(s)ORA,[m]DescriptionOperationAffectedflag(s) Rev.2.1133December29,2008 HT46R23/HT46C23ORA,xDescriptionOperationAffectedflag(s)ORMA,[m]DescriptionOperationAffectedflag(s)RETDescriptionOperationAffectedflag(s)RETA,xDescriptionOperationAffectedflag(s)RETIDescription LogicalORimmediatedatatoACC DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalORop-eration.TheresultisstoredintheAccumulator.ACC¬ACC²OR²xZ LogicalORACCtoDataMemory DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalORoper-ation.TheresultisstoredintheDataMemory.[m]¬ACC²OR²[m]Z Returnfromsubroutine TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesatthere-storedaddress. ProgramCounter¬StackNone ReturnfromsubroutineandloadimmediatedatatoACC TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecifiedimmediatedata.Programexecutioncontinuesattherestoredaddress.ProgramCounter¬StackACC¬xNone Returnfrominterrupt TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbyset-tingtheEMIbit.EMIisthemasterinterruptglobalenablebit.IfaninterruptwaspendingwhentheRETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbe-forereturningtothemainprogram.ProgramCounter¬StackEMI¬1None RotateDataMemoryleft ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. [m].(i+1)¬[m].i;(i=0~6)[m].0¬[m].7None RotateDataMemoryleftwithresultinACC ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryre-mainunchanged. ACC.(i+1)¬[m].i;(i=0~6)ACC.0¬[m].7None OperationAffectedflag(s)RL[m]DescriptionOperationAffectedflag(s)RLA[m]Description OperationAffectedflag(s) Rev.2.1134December29,2008 HT46R23/HT46C23RLC[m]DescriptionOperation RotateDataMemoryleftthroughCarry ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.[m].(i+1)¬[m].i;(i=0~6)[m].0¬CC¬[m].7C RotateDataMemoryleftthroughCarrywithresultinACC DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacestheCarrybitandtheoriginalcarryflagisrotatedintothebit0.TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremainunchanged.ACC.(i+1)¬[m].i;(i=0~6)ACC.0¬CC¬[m].7C RotateDataMemoryright ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7. [m].i¬[m].(i+1);(i=0~6)[m].7¬[m].0None RotateDataMemoryrightwithresultinACC DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0ro-tatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremainunchanged.ACC.i¬[m].(i+1);(i=0~6)ACC.7¬[m].0None RotateDataMemoryrightthroughCarry ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.[m].i¬[m].(i+1);(i=0~6)[m].7¬CC¬[m].0C RotateDataMemoryrightthroughCarrywithresultinACC DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0re-placestheCarrybitandtheoriginalcarryflagisrotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremainunchanged.ACC.i¬[m].(i+1);(i=0~6)ACC.7¬CC¬[m].0C Affectedflag(s)RLCA[m]Description Operation Affectedflag(s)RR[m]DescriptionOperationAffectedflag(s)RRA[m]Description OperationAffectedflag(s)RRC[m]DescriptionOperation Affectedflag(s)RRCA[m]Description Operation Affectedflag(s) Rev.2.1135December29,2008 HT46R23/HT46C23SBCA,[m]Description SubtractDataMemoryfromACCwithCarry ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagaresub-tractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.ACC¬ACC-[m]-COV,Z,AC,C SubtractDataMemoryfromACCwithCarryandresultinDataMemory ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagaresub-tractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthere-sultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.[m]¬ACC-[m]-COV,Z,AC,C SkipifdecrementDataMemoryis0 ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.[m]¬[m]-1Skipif[m]=0None SkipifdecrementDataMemoryiszerowithresultinACC ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,thefollowinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecifiedDataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummyin-structionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.ACC¬[m]-1SkipifACC=0None SetDataMemory EachbitofthespecifiedDataMemoryissetto1.[m]¬FFHNone SetbitofDataMemory BitiofthespecifiedDataMemoryissetto1.[m].i¬1None OperationAffectedflag(s)SBCMA,[m]Description OperationAffectedflag(s)SDZ[m]Description OperationAffectedflag(s)SDZA[m]Description OperationAffectedflag(s)SET[m]DescriptionOperationAffectedflag(s)SET[m].iDescriptionOperationAffectedflag(s) Rev.2.1136December29,2008 HT46R23/HT46C23SIZ[m]Description SkipifincrementDataMemoryis0 ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.[m]¬[m]+1Skipif[m]=0None SkipifincrementDataMemoryiszerowithresultinACC ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,thefollowinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecifiedDataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummyin-structionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.ACC¬[m]+1SkipifACC=0None SkipifbitiofDataMemoryisnot0 IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthisre-quirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Skipif[m].i¹0None SubtractDataMemoryfromACC ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.ACC¬ACC-[m]OV,Z,AC,C SubtractDataMemoryfromACCwithresultinDataMemory ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.TheresultisstoredintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.[m]¬ACC-[m]OV,Z,AC,C SubtractimmediatedatafromACC TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumu-lator.TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnega-tive,theCflagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.ACC¬ACC-xOV,Z,AC,C OperationAffectedflag(s)SIZA[m]Description OperationAffectedflag(s)SNZ[m].iDescription OperationAffectedflag(s)SUBA,[m]Description OperationAffectedflag(s)SUBMA,[m]Description OperationAffectedflag(s)SUBA,xDescription OperationAffectedflag(s) Rev.2.1137December29,2008 HT46R23/HT46C23SWAP[m]DescriptionOperationAffectedflag(s)SWAPA[m]DescriptionOperationAffectedflag(s)SZ[m]Description SwapnibblesofDataMemory Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.[m].3~[m].0«[m].7~[m].4None SwapnibblesofDataMemorywithresultinACC Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.TheresultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.ACC.3~ACC.0¬[m].7~[m].4ACC.7~ACC.4¬[m].3~[m].0None SkipifDataMemoryis0 IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruc-tion. Skipif[m]=0None SkipifDataMemoryis0withdatamovementtoACC ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero,thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruc-tionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.ACC¬[m]Skipif[m]=0None SkipifbitiofDataMemoryis0 IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisre-quirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Skipif[m].i=0None Readtable(currentpage)toTBLHandDataMemory Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.[m]¬programcode(lowbyte)TBLH¬programcode(highbyte)None Readtable(lastpage)toTBLHandDataMemory Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.[m]¬programcode(lowbyte)TBLH¬programcode(highbyte)None OperationAffectedflag(s)SZA[m]Description OperationAffectedflag(s)SZ[m].iDescription OperationAffectedflag(s)TABRDC[m]DescriptionOperationAffectedflag(s)TABRDL[m]DescriptionOperationAffectedflag(s) Rev.2.1138December29,2008 HT46R23/HT46C23XORA,[m]DescriptionOperationAffectedflag(s)XORMA,[m]DescriptionOperationAffectedflag(s)XORA,xDescriptionOperationAffectedflag(s) LogicalXORDataMemorytoACC DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXORop-eration.TheresultisstoredintheAccumulator.ACC¬ACC²XOR²[m]Z LogicalXORACCtoDataMemory DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXORop-eration.TheresultisstoredintheDataMemory.[m]¬ACC²XOR²[m]Z LogicalXORimmediatedatatoACC DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXORoperation.TheresultisstoredintheAccumulator.ACC¬ACC²XOR²xZ Rev.2.1139December29,2008 HT46R23/HT46C23PackageInformation 24-pinSKDIP(300mil)OutlineDimensions Fig1.FullLeadPackagesFig2.1/2LeadPackages ·MS-001d(seefig1) SymbolABCDEFGHI ·MS-001d(seefig2) Dimensionsinmil Min.12302401151151445¾300¾ Nom.¾¾¾¾¾¾100¾¾ Max.12802801951502270¾325430 SymbolABCDEFGHI Dimensionsinmil Min.11602401151151445¾300¾ Nom.¾¾¾¾¾¾100¾¾ Max.11952801951502270¾325430 Rev.2.1140December29,2008 HT46R23/HT46C23·MO-095a(seefig2) SymbolABCDEFGHI Dimensionsinmil Min.11452751201101445¾300¾ Nom.¾¾¾¾¾¾100¾¾ Max.11852951501502260¾325430 Rev.2.1141December29,2008 HT46R23/HT46C2328-pinSKDIP(300mil)OutlineDimensions SymbolABCDEFGHI Dimensionsinmil Min.13752781251251650¾295¾ Nom.¾¾¾¾¾¾100¾¾ Max.13952981351452070¾315375 Rev.2.1142December29,2008 HT46R23/HT46C2324-pinSOP(300mil)OutlineDimensions ·MS-013 SymbolABCC¢DEFGHa Dimensionsinmil Min.39325612598¾¾41680° Nom.¾¾¾¾¾50¾¾¾¾ Max.41930020613104¾1250138° Rev.2.1143December29,2008 HT46R23/HT46C2328-pinSOP(300mil)OutlineDimensions ·MS-013 SymbolABCC¢DEFGHa Dimensionsinmil Min.39325612697¾¾41680° Nom.¾¾¾¾¾50¾¾¾¾ Max.41930020713104¾1250138° Rev.2.1144December29,2008 HT46R23/HT46C23ProductTapeandReelSpecifications ReelDimensions SOP24W SymbolABCDT1T2 Description ReelOuterDiameterReelInnerDiameterSpindleHoleDiameterKeySlitWidth SpaceBetweenFlangeReelThickness Dimensionsinmm 330.0±1.0100.0±1.513.0+0.5/-0.22.0±0.524.8+0.3/-0.230.2±0.2 SOP28W(300mil) SymbolABCDT1T2 Description ReelOuterDiameterReelInnerDiameterSpindleHoleDiameterKeySlitWidth SpaceBetweenFlangeReelThickness Dimensionsinmm 330.0±1.0100.0±1.513.0+0.5/-0.22.0±0.524.8+0.3/-0.230.2±0.2 Rev.2.1145December29,2008 HT46R23/HT46C23CarrierTapeDimensions SOP24W SymbolWPEFDD1P0P1A0B0K0tC SOP28W SymbolWPEFDD1P0P1A0B0K0tC CavityPitchPerforationPosition CavitytoPerforation(WidthDirection)PerforationDiameterCavityHoleDiameterPerforationPitch CavitytoPerforation(LengthDirection)CavityLengthCavityWidthCavityDepth CarrierTapeThicknessCoverTapeWidth Description CarrierTapeWidth Dimensionsinmm 24.0±0.312.0±0.11.75±0.1011.5±0.11.5+0.1/-0.01.50+0.25/-0.00 4.0±0.12.0±0.110.85±0.1018.34±0.102.97±0.100.35±0.0121.3±0.1 CavityPitchPerforationPosition CavitytoPerforation(WidthDirection)PerforationDiameterCavityHoleDiameterPerforationPitch CavitytoPerforation(LengthDirection)CavityLengthCavityWidthCavityDepth CarrierTapeThicknessCoverTapeWidth Description CarrierTapeWidth Dimensionsinmm 24.0±0.312.0±0.11.75±0.111.5±0.11.55+0.10/-0.001.50+0.25/-0.00 4.0±0.12.0±0.110.9±0.115.9±0.13.1±0.10.35±0.0521.3±0.1 Rev.2.1146December29,2008 HT46R23/HT46C23HoltekSemiconductorInc.(Headquarters) No.3,CreationRd.II,SciencePark,Hsinchu,TaiwanTel:886-3-563-1999Fax:886-3-563-1189http://www.holtek.com.tw HoltekSemiconductorInc.(TaipeiSalesOffice) 4F-2,No.3-2,YuanQuSt.,NankangSoftwarePark,Taipei115,TaiwanTel:886-2-2655-7070Fax:886-2-2655-7373 Fax:886-2-2655-7383(Internationalsaleshotline) HoltekSemiconductorInc.(ShanghaiSalesOffice) GRoom,3Floor,No.1Building,No.2016Yi-ShanRoad,MinhangDistrict,Shanghai,China201103Tel:86-21-5422-4590Fax:86-21-5422-4705http://www.holtek.com.cn HoltekSemiconductorInc.(ShenzhenSalesOffice) 5F,UnitA,ProductivityBuilding,GaoxinM2nd,MiddleZoneOfHigh-TechIndustrialPark,ShenZhen,China518057Tel:86-755-8616-9908,86-755-8616-9308Fax:86-755-8616-9722 HoltekSemiconductorInc.(BeijingSalesOffice) Suite1721,JinyuTower,A129WestXuanWuMenStreet,XichengDistrict,Beijing,China100031Tel:86-10-6641-0030,86-10-6641-7751,86-10-6641-7752Fax:86-10-6641-0125 HoltekSemiconductorInc.(ChengduSalesOffice) 709,Building3,ChampagnePlaza,No.97DongdaStreet,Chengdu,Sichuan,China610016Tel:86-28-6653-6590Fax:86-28-6653-6591 HoltekSemiconductor(USA),Inc.(NorthAmericaSalesOffice)46729FremontBlvd.,Fremont,CA94538,USATel:1-510-252-9880Fax:1-510-252-9885http://www.holtek.com CopyrightÓ2008byHOLTEKSEMICONDUCTORINC. TheinformationappearinginthisDataSheetisbelievedtobeaccurateatthetimeofpublication.However,Holtekas-sumesnoresponsibilityarisingfromtheuseofthespecificationsdescribed.TheapplicationsmentionedhereinareusedsolelyforthepurposeofillustrationandHoltekmakesnowarrantyorrepresentationthatsuchapplicationswillbesuitablewithoutfurthermodification,norrecommendstheuseofitsproductsforapplicationthatmaypresentarisktohumanlifeduetomalfunctionorotherwise.Holtek¢sproductsarenotauthorizedforuseascriticalcomponentsinlifesupportdevicesorsystems.Holtekreservestherighttoalteritsproductswithoutpriornotification.Forthemostup-to-dateinformation,pleasevisitourwebsiteathttp://www.holtek.com.tw. Rev.2.1147December29,2008 因篇幅问题不能全部显示，请点此查看更多更全内容