基本功能要求：
设计一个电子时钟，要求可以显示时、分、秒，用户可以通过按键来设置时间。
扩展功能要求：
秒表功能，闹钟功能，调整数码管的亮度。
试验箱设置：
1、 选择模式7（见附图1）;
2、 数码管8左边的跳线选择CLOSE(数码管连接关系看课本406
页图F-8);
整体原理图：
管
脚
分
配
图
：
本设计的原理图：
报告具体内容：
一．设计目的
设计一个电子时钟，可以显示时、分、秒，用户可以设置时间。
扩展功能为秒表功能，闹钟功能，调整数码管的亮度。
二．设计内容
1.整体功能
》分模块设置调表，跑表，闹钟，speaker，秒表，走表模块设置，最后用一个三选一选择器对各模块进行选择，最后输入到扫描模块中进行输出。
》调表模块：1.通过键1键4对分秒时进行位选择和位加，将调表的输出分别接到跑表和模式选择中，接到跑表中是设置完时间后可以继续计时输出，接到模式选择中，可以通过模式2输出调表设置的时间。 》闹钟设置：同设置模块，键1键4是对位选跟位加，而闹钟一定要接到speaker中，与输入到speaker中的跑表对比，当走表走到设置的时间时，speaker会发出响声。
》speaker：将speaker的输出接到板子上的speaker中，当一定要接一个clk输出，speaker才能发出震动输出响声。
》跑表模块：用键1 来给跑表覆初值，通过输入1HZ的时钟来加数，正常走表的输出要接在模式选择上，通过模式1来进行选择输出走表功能。
》秒表功能：语言跟走表相似，但开始是，要先对秒表用信号覆初值为0，通过键1来清零，秒表的输出要接在模式选择上，通过模式3对秒表进行输出。
》模式选择：模式选择的实现是通过一个三选一选择器对各功能进行选择，将输出接到位扫描器上，通过位选和段选来输出。
》扫描输出：
通过对左侧的段选输入对数码管的各段进行显示，通过对右侧各位进行选通来达到位选择输出的目的，用10000HZ的频率来刷频就不会看到输出时输出的转换，亮度调节是对通过改变选通位选信号的不同占空比来达到调节亮度的目的，键5 是用作不同的占空比输出，在调节占空比时是对输入信号低位和高位进行占空比调节，具体见程序代码中。
三 电子钟的整体VHDL 语言描述
分频器的vhdl语言
library ieee;
use ieee.std_logic_1164.all; --分频 use ieee.std_logic_unsigned.all; entity fenpin is port(
clk:in std_logic;
clkend_100:out std_logic; clkend_10000:out std_logic; clkend_1:out std_logic); end;
architecture behv of fenpin is signal clk1_tmp:std_logic; signal clk100_tmp:std_logic; signal clk10000_tmp:std_logic;
signal cnt5000000:integer range 0 to 5000000; signal cnt50000:integer range 0 to 50000; signal cnt5000:integer range 0 to 500; begin
HZ1: process(clk)
begin --输出1HZ频率，作为跑表时钟
if clk'event and clk='1' then
if cnt5000000<4999999 then
cnt5000000<=cnt5000000+1; else
cnt5000000<=0;
clk1_tmp<=NOT clk1_tmp ; end if; end if;
end process;
HZ100: process(clk) begin
if clk'event and clk='1' then --输出100HZ频率，作为秒表时钟输入
if cnt50000<49999 then
cnt50000<=cnt50000+1; else
cnt50000<=0;
clk100_tmp<=NOT clk100_tmp ; end if; end if;
end process;
HZ1000: process(clk) --输出1000HZ频率，作为扫描输出时钟 begin
if clk'event and clk='1' then if cnt5000<499 then
Cnt5000<=cnt5000+1; else
Cnt5000<=0;
clk10000_tmp<=NOT clk10000_tmp ; end if; end if; end process;
clkend_1<=clk1_tmp; clkend_100<=clk100_tmp;
clkend_10000<=clk10000_tmp; end behv;
>Speaker
library ieee; --闹钟对时输出响声 use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity speaker is
port ( clk_100: in std_logic;
shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:in
integer range 0 to 9;--跑表输入与闹钟设置时间输入来对比输出响声 shishi,shige,fenshi,fenge,miaoshi,miaoge:in integer range 0 to 9; speaker_1 : out std_logic); end entity;
architecture bhv of speaker is begin
process(clk_100,shishi,shige,fenshi,fenge,miaoshi,miaoge,shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2) begin
if shishi2=shishi and shige2=shige and fenshi2=fenshi and fenge2=fenge and miaoshi2=miaoshi and miaoge2=miaoge then --校对时间，时间相同时输出响声
speaker_1<= clk_100; else speaker_1 <='1'; end if; end process; end bhv;
闹钟的vhdl语言
library ieee; --设置闹钟时间来与跑表时间对比产生响声 use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity naozhong is
port(jian4,jian1:in std_logic;
shishi,shige,fenshi,fenge,miaoshi,miaoge:out integer range 0 to 9); end entity;
architecture bhv of naozhong is signal set: integer range 0 to 5;
signal shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1: integer range 0 to 9; begin
U1:process (jian4) --键4是利用加法器对闹钟进行选位 begin
if jian4'event and jian4='1' then if set> 5 then set<= 0;
else set<=set+ 1; end if; end if; end process;
U2:process(jian1,set)
begin --键1 是通过闹钟选好位后再对每一位相加
if jian1'event and jian1='1' then case set is when 0 =>
if miaoge1 =9 then miaoge1<=0;
else miaoge1<=miaoge1+1; end if;
when 1=>
if miaoshi1 =5 then miaoshi1<=0;
else miaoshi1<=miaoshi1+1; end if;
when 2=>
if fenge1 =9 then fenge1<=0;
else fenge1<=fenge1+1; end if;
when 3 =>
if fenshi1 =5 then fenshi1<=0;
else fenshi1<=fenshi1+1; end if;
when 4 =>
if shige1 =9 then shige1<=0;
else shige1<=shige1+1; end if;
when 5 =>
if shishi1 =2 then shishi1<=0;
else shishi1<=shishi1+1; end if; when others => null ;
end case; end if;
end process;
miaoge<=miaoge1; miaoshi<=miaoshi1; fenge<=fenge1; fenshi<=fenshi1; shige<=shige1; shishi<=shishi1; end bhv;
调表的vhdl语言
library ieee; --设置当前时间 use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity settime is
port(jian4,jian1:in std_logic;
shishi,shige,fenshi,fenge,miaoshi,miaoge:out integer range 0 to 9); end entity;
architecture bhv of settime is signal set: integer range 0 to 5;
signal shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1: integer range 0 to 9; begin
U1:process (jian4) --键4键1是用来对时分秒进行选位与
Begin 加位的 if jian4'event and jian4='1' then if set> 5 then set<= 0;
else set<=set+ 1; end if; end if; end process;
U2:process(jian1,set) begin
if jian1'event and jian1='1' then case set is when 0 =>
if miaoge1 =9 then miaoge1<=0;
else miaoge1<=miaoge1+1;
end if;
when 1=>
if miaoshi1 =5 then miaoshi1<=0;
else miaoshi1<=miaoshi1+1; end if;
when 2=>
if fenge1 =9 then fenge1<=0;
else fenge1<=fenge1+1; end if;
when 3 =>
if fenshi1 =5 then fenshi1<=0;
else fenshi1<=fenshi1+1; end if;
when 4 =>
if shige1 =9 then shige1<=0;
else shige1<=shige1+1; end if;
when 5 =>
if shishi1 =2 then shishi1<=0;
else shishi1<=shishi1+1; end if; when others => null ; end case; end if;
end process;
miaoge<=miaoge1; miaoshi<=miaoshi1; fenge<=fenge1;
fenshi<=fenshi1; shige<=shige1; shishi<=shishi1;
end bhv;
走表的vhdl语言
library ieee; --跑表 use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity paobiao is port(clk:in std_logic; jian1:in std_logic;
shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9; --跑表初始输入
shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:out integer range 0 to 9); --跑表输出
end entity;
architecture bhv of paobiao is
signal shi,fen,miao:integer range 0 to 100; begin
process(clk,jian1,shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1) begin
if jian1='1' then
shi<=shishi1*10+shige1; --将表的初始时间赋到信号中 fen<=fenshi1*10+fenge1;
miao<=miaoshi1*10+miaoge1; elsif clk'event and clk='1' then if miao=59 then
miao<=0; --对通过加法器来对分时秒依次相加
fen<=fen+1; elsif fen>59 then fen<=0; shi<=shi+1; elsif shi>23 then shi<=0; else miao<=miao+1; end if;
else null;
end if; end process;
miaoge2<=miao rem 10; --用rem和除号对个位和十位进行取余和取模
miaoshi2<=miao/10; fenge2<=fen rem 10; fenshi2<=fen/10; shige2<=shi rem 10; shishi2<=shi/10; end;
秒表的vhdl语言
library ieee; --秒表 use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity miaobiao is --键1作为复位端输入 port(clk_100:in std_logic; --秒表要用100HZ频率 jian1:in std_logic;
haomiaoshi2,haomiaoge2,fenshi2,fenge2,miaoshi2, miaoge2:out integer range 0 to 9); end entity;
architecture bhv of miaobiao is
signal haomiaoshi1,haomiaoge1,fenshi1,fenge1，
miaoshi1,miaoge1 :integer range 0 to 9 ; signal haomiao,fen,miao:integer range 0 to 100; begin
haomiaoshi1<=0;
haomiaoge1 <=0; --给秒表赋初值为0 fenshi1<=0; fenshi1<=0; miaoshi1<=0; miaoge1<=0;
process(clk_100,jian1,haomiaoshi1,haomiaoge1,fenshi1,fenge1,miaoshi1,miaoge1) begin
if clk_100'event and clk_100='1' then if jian1='1' then --同跑表功能
haomiao<=haomiaoshi1*10+haomiaoge1; fen<=fenshi1*10+fenge1; miao<=miaoshi1*10+miaoge1; elsif haomiao=99 then haomiao<=0; miao<=miao+1; elsif miao>59 then miao<=0; fen<=fen+1; elsif fen>59 then fen<=0;
else haomiao<= haomiao+1; end if; end if; end process;
haomiaoge2<=haomiao rem 10; haomiaoshi2<=haomiao/10; miaoge2<=miao rem 10; miaoshi2<=miao/10; fenge2<=fen rem 10; fenshi2<=fen/10; end;
模式选择的vhdl语言
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity moshi is
port( jian8:in std_logic;
pshishi1,pshige1,pfenshi1,pfenge1,pmiaoshi1,
pmiaoge1:in integer range 0 to 9; --跑表输入 sshishi2,sshige2,sfenshi2,sfenge2,smiaoshi2,
smiaoge2:in integer range 0 to 9; --调时输入 fenshi,fenge,miaoshi,miaoge,haomiaoshi,
haomiaoge:in integer range 0 to 9; --秒表输入 a0,a1,a3,a4,a6,a7:inout integer range 0 to 9); end entity;
architecture bhv of moshi is --通过加法器来进行选择不同模式
signal moshi_1 :integer range 0 to 3; begin
u1:process(jian8) begin
if jian8 'event and jian8='1' then if moshi_1 >3 then moshi_1 <= 0;
else moshi_1<=moshi_1+1; end if; else null; end if; end process;
u2:process (moshi_1) --模式选择输出 begin
case moshi_1 is
when 0 => a0<=pshishi1;a1<=pshige1;a3<=pfenshi1;a4<=pfenge1; a6<=pmiaoshi1;a7<=pmiaoge1; --跑表输出 when 1=> a0<=sshishi2;a1<=sshige2;a3<=sfenshi2;a4<=sfenge2; a6<=smiaoshi2;a7<=smiaoge2; --调表输出 when 2=> a0<=fenshi;a1<=fenge;a3<=miaoshi;a4<=miaoge; a6<=haomiaoshi;a7<=haomiaoge; --秒表输出 when others =>null; end case; end process; end bhv;
扫描输出加亮度显示vhdl语言
library ieee; --扫描显示 use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity saomiao is port(
clk_1000:in std_logic; jian5:in std_logic;
a0,a1,a3,a4,a6,a7:in integer range 0 to 9;
dx:out std_logic_vector(6 downto 0); --位控制位输出 wx:out std_logic_vector(7 downto 0)); --段控制位输出 end entity;
architecture bhv of saomiao is
signal cnt32 :std_logic_vector(4 downto 0); signal a :integer range 0 to 15; signal cnt3:integer range 0 to 3; signal cnt4:integer range 0 to 3;
signal count: std_logic; begin
b1: process(cnt32,a0,a1,a3,a4,a6,a7) begin
case cnt32(4 downto 2) is -- 段选输出，count为不同占空比输入
when \"000\" => wx<= \"0000000\"&(count);a<=a0; when \"001\" => wx<= \"000000\"&(count)&'0';a<=a1; when \"010\" => wx<= \"00000\"&(count)&\"00\";a<=15; when \"011\" => wx<= \"0000\"&(count)&\"000\";a<=a3; when \"100\" => wx<= \"000\"&(count)&\"0000\";a<=a4; when \"101\" => wx<= \"00\"&(count)&\"00000\";a<=15; when \"110\" => wx<= '0'&(count)&\"000000\";a<=a6; when \"111\" => wx<= (count)&\"0000000\";a<=a7; when others => null; end case; end process ;
b2:process(clk_10000) --加法器来控制段选输出 begin
if clk_10000'event and clk_10000 ='1' then cnt32 <= cnt32+1; else null; end if;
end process ; b3:process(a) begin case a is
when 0 => dx<= \"0111111\"; --位选输出 when 1 => dx<= \"0000110\"; when 2 => dx<= \"1011011\"; when 3 => dx<= \"1001111\"; when 4 => dx<= \"1100110\"; when 5 => dx<= \"1101101\"; when 6 => dx<= \"1111101\"; when 7 => dx<= \"0000111\"; when 8 => dx<= \"1111111\"; when 9 => dx<= \"1101111\"; when 10 => dx<= \"1110111\"; when 11 => dx<= \"1111100\"; when 12 => dx<= \"0111001\"; when 13 => dx<= \"1011110\"; when 14 => dx<= \"1111001\"; when 15 => dx<= \"1000000\"; when others => null;
end case; end process ;
b4:process (jian5) -- 键5 作为信号端对不同亮度进行选择输出 begin
if jian5'event and jian5='1' then if cnt3 > 3 then cnt3<= 0;
else cnt3<=cnt3+1; end if; end if;
end process; b5:process (clk_10000) begin
if clk_10000'event and clk_10000='1' then if cnt4 =3 then cnt4<= 0;
else cnt4<=cnt4+1; end if; end if;
end process;
b6: process (cnt3,cnt4) --cnt3来对不同亮度进行选择输出，cnt4是对count调节不同占空比 begin
case cnt3 is
when 0 =>
if cnt4=0 then
count<= '1'; --占空比1：0=1：3 else count<='0'; end if;
when 1 => if cnt4<2 then --占空比1：0=2：2 count<='1';
else count<='0'; end if;
when 2 => if cnt4<3 then --占空比1：0=3：1 count<='1';
else count <='0'; end if;
when 3 => if cnt4<4 then --占空比1：0=4：0 count<='1';
else count <='0'; end if; end case; end process; end bhv;
整体例化的vhdl语言
library ieee; --主程序 use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity lihua is
port(clk_10m:in std_logic;
jian1,jian4,jian5,jian8,jian7:in std_logic; wx1:out std_logic_vector(7 downto 0); dx1:out std_logic_vector(6 downto 0); speaker_1:out std_logic); end entity;
architecture bhv of lihua is component saomiao is
PORT( CLK_1000,jian5:IN STD_LOGIC; a0,a1,a3,a4,a6,a7 : IN INTEGER RANGE 0 TO 9; --时钟输入
dX: OUT STD_LOGIC_VECTOR(6 downto 0); --段控制信号；
wX: OUT STD_LOGIC_VECTOR(7 downto 0)); --位控制信号；
end component;
component naozhong is
port(jian4,jian1:in std_logic; --键 4控制闹钟设置时间选位，键1控制各位的加法
shishi,shige,fenshi,fenge,miaoshi, miaoge:out integer range 0 to 9); end component;
component speaker is
port ( clk_100: in std_logic;
shishi2,shige2,fenshi2,fenge2,miaoshi2,
miaoge2:in integer range 0 to 9; shishi,shige,fenshi,fenge,miaoshi, miaoge:in integer range 0 to 9; speaker_1 : out std_logic);
end component; component miaobiao is
port(clk_100:in std_logic; --键1为置位端输入 jian1:in std_logic;
haomiaoshi2,haomiaoge2,fenshi2,fenge2,miaoshi2, miaoge2:out integer range 0 to 9);
end component; component moshi is port( jian8:in std_logic;
pshishi1,pshige1,pfenshi1,pfenge1,pmiaoshi1, pmiaoge1:in integer range 0 to 9; --跑表输入 sshishi2,sshige2,sfenshi2,sfenge2,
smiaoshi2,smiaoge2:in integer range 0 to 9; --调时输入 fenshi,fenge,miaoshi,miaoge,haomiaoshi,
haomiaoge:in integer range 0 to 9; --秒表输入 a0,a1,a3,a4,a6,a7:inout integer range 0 to 9); end component;
component settime is
--键 4控制闹钟设置时间选位，键1控制各位的加法 port(jian4,jian1:in std_logic;
shishi,shige,fenshi,fenge,miaoshi, miaoge:out integer range 0 to 9);
end component;
component fenpin is port(
clk:in std_logic; --三种不同频率输出
clkend_100:out std_logic; clkend_10000:out std_logic; clkend_1:out std_logic);
end component;
component paobiao is
port(clk:in std_logic; --键1作为置位端输入
jian1:in std_logic;
shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9; shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:out integer range 0 to 9);
end component; --信号 signal shishisp,shigesp,fenshisp,fengesp,
miaoshisp,miaogesp: integer range 0 to 9; signal shishipsp,shigepsp,fenshipsp,fengepsp,
miaoshipsp,miaogepsp: integer range 0 to 9; signal shishinsp,shigensp,fenshinsp,fengensp,
miaoshinsp,miaogensp: integer range 0 to 9; signal shishipm,shigepm,fenshipm,fengepm,
miaoshipm,miaogepm: integer range 0 to 9; signal shishism,shigesm,fenshism,fengesm,miaoshism, miaogesm: integer range 0 to 9;
signal haomiaoshimm,haomiaogemm,fenshimm,fengemm, miaoshimm,miaogemm: integer range 0 to 9; signal shishims,shigems,fenshims,fengems,miaoshims, miaogems: integer range 0 to 9; signal clk1f,clk100f,clk10000f: std_logic;
signal a0ms,a1ms,a3ms,a4ms,a6ms,a7ms: integer range 0 to 9; begin
s1: naozhong port map ( jian1 =>jian1,jian4=>jian4,
shishi=>shishinsp,shige=>shigensp,
fenshi=>fenshinsp, --闹钟例化，闹钟输出接到模式输入和speaker输入上
fenge=>fengensp,miaoshi=>miaoshinsp,miaoge=>miaogensp);
s3: saomiao port map ( jian5=>jian5,clk_1000=>clk1000f, a0=>a7ms,a1=>a6ms,a3=>a4ms,
a4=>a3ms,a6=>a1ms,a7=>a0ms,wx=>wx1,dx=>dx1); --扫描例化
s4: miaobiao port map
(clk_100=>clk100f,jian1=>jian1,haomiaoshi2=>haomiaoshimm,
haomiaoge2=>haomiaogemm, --秒表例化
fenshi2=>fenshimm,fenge2=>fengemm,miaoshi2=>miaoshimm,miaoge2=>miaogemm);
s5 moshi port map
(jian8=>jian8,pshishi1=>shishipm,pshige1=>shigepm,pfenshi1=>fenshipm, pfenge1=>fengepm,pmiaoshi1=>miaoshipm,
pmiaoge1=>miaogepm, --模式选择输出
sshishi2=>shishisp,sshige2=>shigesp,sfenshi2=>fenshisp,sfenge2=>fengesp, smiaoshi2=>miaoshisp,smiaoge2=>miaogesp,
fenshi=>fenshimm,fenge=>fenshimm,miaoshi=>miaoshimm,
miaoge=>miaogemm,haomiaoshi=>haomiaoshimm,haomiaoge=>haomiaogemm,
a0=>a0ms,a1=>a1ms,a3=>a3ms,a4=>a4ms,a6=>a6ms,a7=>a7ms);
s6: settime port map (jian4=>jian4,jian1=>jian1,shishi=>shishisp,
shige=>shigesp,fenshi=>fenshisp, --对调表例化
fenge=>fengesp,miaoshi=>miaoshisp,miaoge=>miaogesp);
s7: fenpi port map
(clk=>clk_10m,clkend_1=>clk1f,clkend_100=>clk100f,clkend_10000=>clk10000f);
s8: paobiao port map (jian1=>jian7,clk=>clk1f,shishi1=>shishisp,
shige1=>shigesp,fenshi1=>fenshisp,
fenge1=>fengesp,miaoshi1=>miaoshisp,miaoge1=>miaogesp,
shishi2=>shishipm,shige2=>shigepm, fenshi2=>fenshipm,fenge2=>fengepm,
miaoshi2=>miaoshipm,miaoge2=>miaogepm); s9:speaker port map
(clk_100=>clk100f,speaker_1=>speaker_1,shishi2=>shishipsp,
shige2=>shigepsp,fenshi2=>fenshipsp, --闹钟调节于跑表对比输出响声
fenge2=>fengepsp,miaoshi2=>miaoshipsp,miaoge2=>miaogepsp,
shishi=>shishinsp,shige=>shigensp,
fenshi=>fenshinsp,fenge=>fengensp,miaoshi=>miaoshinsp,miaoge=>miaogensp);
end bhv;
EDA课程设计报告
——数字钟设计
班 级：通信11级二班 学 号：20115135 姓 名：赵俊新
五、实验心得：
本次课程设计是通过所学的EDA知识，自主设计使用物品，将所学的知识运用到实处，感觉收获很大，以前学的时候都是学的理论上的知识，并没有运用到实际做具体的功能器件上来，通过这次的课程设计使我将理论的知识联系到实际运用中来，巩固了以前学习的知识，并且有了新的收获，进一步熟悉了软件运用和实验箱的使用，增强了自我动手能力。 EDA课程已经结课一段时间，好多 掌握的不够牢固，所以在实验过程中要经常翻阅书本查询相关知识，实验的过程也将书本的知识进一步强化，对书本的知识有了新的认识，受益匪浅。在程序设计过程中容易将各个复合语句的范围用错，从而出现意想不到的结果，逻辑出现紊乱，有时是漏掉了某些语句或者是一些语法错误，这些在编译的时候都会有相应的出错提示，顺着提示去改正相对比较容易，不过也出现过几次错误出现的地方和提示出错的地方不一致，费了很大力气才解决，还有一种就是，编译可以通过，但是结果不与预想的一致，一般进程process…end process不会出错，原因主要是进程中的逻辑顺序或嵌套没有安排好，比如if…else……end if语句，如果if语句结束的位置用错，即end if的位置不对，不会提示出错但是不能达到想要的结果，这就需要从头认真分析各逻辑关系，重新考虑end if位置，总之课程设计虽然辛苦，但是却有其中的乐趣，尤其是解决问题后的成就感，学以致用，感觉很充实。EDA是现代信息社会里很有用的一门学科，以后一定会再次用到，现在打好基础，为以后的学习和工作奠定基础，培养兴趣。
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