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Sub-Class: More specifically identifies the device function.
Interface: Defines a specific register-level programming interface, if any, allowingdevice-independent software to interface with the device.
Class code encoding can be found at the PCI SIG website.
Class Code Look-up Assistant
The Class Code Look-up Assistant provides the Base Class, Sub-Class and Interface values for a selected general function of a device. This Look-up Assistant tool only displays the three values for a selected function. You must enter the values in Class Code for these values to be translated into device settings.
Base Address Registers (PF0 and PF1) Tab
The Base Address Registers (BARs) page sets the base address register space for the Endpoint configuration. Each BAR (0 through 5) configures the BAR Aperture Size and Control attributes of the physical function.
Base Address Register Overview
In Endpoint configuration, the core supports up to six 32-bit BARs or three 64-bit BARs, and the Expansion read-only memory (ROM) BAR. In Root Port configuration, the core supports up to two 32-bit BARs or one 64-bit BAR, and the Expansion ROM BAR. BARs can be one of two sizes:••
32-bit BARs: The address space can be as small as 128 bytes or as large as 2 gigabytes.Used for Memory to I/O.
64-bit BARs: The address space can be as small as 128 bytes or as large as 256gigabytes. Used for Memory only.
All BAR registers share these options:••
Checkbox: Click the checkbox to enable the BAR; deselect the checkbox to disable theBAR.
Type: BARs can either be I/O or Memory.
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I/O: I/O BARs can only be 32-bit; the Prefetchable option does not apply to I/OBARs. I/O BARs are only enabled for the Legacy PCI Express Endpoint core.Memory: Memory BARs can be either 64-bit or 32-bit and can be prefetchable.When a BAR is set as 64 bits, it uses the next BAR for the extended address space and makes the next BAR inaccessible.
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Size: The available Size range depends on the PCIe Device/Port Type and the Type ofBAR selected. Table4-4 lists the available BAR size ranges.
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Table 4-4:
BAR Size Ranges for Device Configuration
BAR Type
32-bit Memory64-bit Memory32-bit Memory
Legacy PCI Express Endpoint
64-bit Memory
I/O32-bit Memory
Root port of PCI Express Root Complex
64-bit Memory
I/O
PCIe Device / Port Type
PCI Express Endpoint
BAR Size Range
128 bytes (B) – 2 gigabytes (GB)
128 B – 256 GB128 B – 2 GB128 B – 256 GB16 B – 2 GB4 B – 2 GB4 B – 8 GB16 B – 2 GB
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Prefetchable: Identifies the ability of the memory space to be prefetched.Value: The value assigned to the BAR based on the current selections.
For more information about managing the Base Address Register settings, see Managing Base Address Register Settings.
Expansion ROM Base Address Register
If selected, the Expansion ROM is activated and can be a value from 2 KB to 4 GB. According to the PCI 3.0 Local Bus Specification [Ref2], the maximum size for the Expansion ROM BAR should be no larger than 16 MB. Selecting an address space larger than 16 MB can result in a non-compliant core.
Managing Base Address Register Settings
Memory, I/O, Type, and Prefetchable settings are handled by setting the appropriate settings for the desired base address register.
Memory or I/O settings indicate whether the address space is defined as memory or I/O. The base address register only responds to commands that access the specified address space. Generally, memory spaces less than 4 KB in size should be avoided. The minimum I/O space allowed is 16 bytes; use of I/O space should be avoided in all new designs.Prefetchability is the ability of memory space to be prefetched. A memory space is
prefetchable if there are no side effects on reads (that is, data is not destroyed by reading, as from a RAM). Byte-write operations can be merged into a single double word write, when applicable.
When configuring the core as an Endpoint for PCIe (non-Legacy), 64-bit addressing must be supported for all BARs (except BAR5) that have the prefetchable bit set. 32-bit addressing is permitted for all BARs that do not have the prefetchable bit set. The prefetchable bit-related requirement does not apply to a Legacy Endpoint. The minimum memory
address range supported by a BAR is 128 bytes for a PCI Express Endpoint and 16 bytes for a Legacy PCI Express Endpoint.
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Chapter 4:Design Flow Steps
Disabling Unused Resources
For best results, disable unused base address registers to conserve system resources. A base address register is disabled by deselecting unused BARs in the Customize IP dialog box.
Legacy/MSI Capabilities Tab
On this page, you set the Legacy Interrupt Settings and MSI Capabilities for all applicable physical and virtual functions.
Legacy Interrupt Settings
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Enable MSI Per Vector Masking: Enables MSI Per Vector Masking Capability of all thePhysical functions enabled.
Note:Enabling this option for individual physical functions is not supported.•
PF0/PF1 Interrupt PIN: Indicates the mapping for Legacy Interrupt messages. Asetting of None indicates that no Legacy Interrupts are used.
MSI Capabilities
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PF0/PF1 Enable MSI Capability Structure: Indicates that the MSI Capability structureexists.
Note:Although it is possible to not enable MSI or MSI-X, the result would be a non-compliantcore. The PCI Express Base Specification [Ref2] requires that MSI, MSI-X, or both be enabled.•
Multiple Message Capable: Selects the number of MSI vectors to request from theRoot Complex.
Advanced Mode Parameters
The following parameters appear on different pages of the IP catalog when Advanced mode is selected for Mode on the Basic page.
Basic Tab
The Basic page for Advanced mode includes some additional settings. The following parameters are on the Basic page when the Advanced mode is selected.
Enable Parity
Enables the Parity feature of the UltraScale IP when checked. The two model parameters AXISTEN_IF_CC_PARITY_CHK and AXISTEN_IF_RQ_PARITY_CHK are set to TRUE. The default value of this parameter is FALSE.
Use the dedicated PERST routing resources
Enables sys_rst dedicated routing for applicable PCIe locations (see Table2-2).
UltraScale Devices Gen3 Block for PCIe v4.4PG156 April 4, 2018
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